DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 255

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 7: External Memory Interfaces in Stratix V Devices
Stratix V External Memory Interface Features
Table 7–3. DLL Reference Clock Input for 5SGXA3 and 5SGXA4 Devices
Table 7–4. DLL Reference Clock Input for 5SGXB5 and 5SGXB6 Devices (Part 1 of 2)
May 2011 Altera Corporation
DLL_TL
DLL_TR
DLL_BR
DLL_BL
DLL_TL
DLL_TR
DLL
DLL
1
CEN_X70_Y76
CEN_X70_Y31
CEN_X70_Y76
CEN_X70_Y71
CEN_X74_Y136
CEN_X74_Y131
CEN_X74_Y136
CEN_X74_Y131
CEN_X0_Y7
CEN_X0_Y2
CEN_X0_Y7
CEN_X0_Y2
Center
Center
If you have a dedicated PLL that only generates the DLL input reference clock, set the
PLL mode to No Compensation to achieve better performance (or the Quartus II
software automatically changes it). Because the PLL does not use any other outputs, it
does not have to compensate for any clock paths.
PLL
PLL
LR_X152_Y93
LR_X152_Y89
LR_X152_Y15
LR_X152_Y11
LR_X0_Y93
LR_X0_Y89
LR_X0_Y15
LR_X0_Y11
LR_X163_Y135
LR_X163_Y131
LR_X0_Y135
LR_X0_Y131
Corner
Left/Right
CLK20P
CLK21P
CLK22P
CLK23P
CLK0P
CLK1P
CLK2P
CLK3P
Left
—
—
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
CLK20P
CLK21P
CLK22P
CLK23P
Left
—
CLK16P
CLK17P
CLK18P
CLK19P
CLK16P
CLK17P
CLK18P
CLK19P
Center
CLK4P
CLK5P
CLK6P
CLK7P
CLK4P
CLK5P
CLK6P
CLK7P
CLKIN
CLK16P
CLK17P
CLK18P
CLK19P
CLK16P
CLK17P
CLK18P
CLK19P
Center
CLKIN
CLK12P
CLK13P
CLK14P
CLK15P
CLK10P
CLK11P
CLK8P
CLK9P
CLK12P
CLK13P
CLK14P
CLK15P
Right
Right
—
—
—
7–11