DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 351

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

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SV51012-1.2
IEEE Std. 1149.6 Boundary-Scan Register
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
May 2011
May 2011
SV51012-1.2
f
This chapter describes the boundary-scan test (BST) features that are supported in
Stratix
Stratix V devices support IEEE Std. 1149.1 and IEEE Std. 1149.6. The IEEE Std. 1149.6
is only supported on the high-speed serial interface (HSSI) transceivers in Stratix V
devices. IEEE Std. 1149.6 enables board-level connectivity checking between
transmitters and receivers that are AC coupled (connected with a capacitor in series
between the source and destination).
This chapter includes the following sections:
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For more information about the following IEEE Std. 1149.1 BST features, refer to the
IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices
the Stratix III Device Handbook:
The boundary-scan cells (BSCs) for HSSI transmitters (GXB_TX[p,n]) and
receivers/input clock buffer (GXB_RX[p,n])/(REFCLK[p,n]) in Stratix V devices are
different from the BSCs for the I/O pins.
“IEEE Std. 1149.6 Boundary-Scan Register” on page 11–1
“BST Operation Control” on page 11–3
“I/O Voltage Support in a JTAG Chain” on page 11–5
“Boundary-Scan Description Language Support” on page 11–6
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®
IEEE Std. 1149.1 BST architecture and circuitry
IEEE Std. 1149.1 boundary-scan register
IEEE Std. 1149.1 BST guidelines
Test access port (TAP) controller state-machine
V devices.
11. JTAG Boundary-Scan Testing in
Stratix V Devices
chapter in volume 1 of
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