DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 44

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: DC and Switching Characteristics for Stratix V Devices
Switching Characteristics
Table 2–19. Transceiver Specifications for Stratix V GX and GS Devices—Preliminary (Part 3 of 3)
May 2011 Altera Corporation
Transmitter
Supported I/O
Standards
Data rate
(Standard PCS)
Data rate (10G PCS)
V
Differential on-chip
termination resistors
Transmitter
Rise time
Fall time
CMU PLL
Supported Data Range
ATX PLL
Supported Data Range
Input Reference Clock
Frequency
Transceiver-FPGA Fabric Interface
Interface speed
Notes to
(1) Speed grades shown in
(2) The reference clock common mode voltage is equal to the V
(3) The device cannot tolerate prolonged operation at this absolute maximum.
(4) The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver Equalization, the
(5) The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.
(6) The input reference clock frequency options depend on the data rate and the device speed grade.
OCM
speed grade. Contact your Altera Sales Representative for the maximum data rate specifications in each speed grade combination offered. For more
information about device ordering codes, refer to the
receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
Description
Symbol/
Table
(5)
(5)
(6)
2–19:
Table 2–19
0.65-V setting
100- setting
120- setting
150- setting
85- setting
post-divider
Conditions
VCO
L=1
L=2
L=4
—
—
—
—
—
—
—
refer to the PMA Speed Grade in the device ordering code. The maximum data rate could be restricted by the Core/PCS
8000
4000
2000
2000
Min
600
100
600
—
30
30
25
Stratix V Device Family Overview
Speed Grade
Commercial
650
Typ
CCR_GXB
—
—
—
—
—
—
—
—
—
—
100
120
150
–1
85
power supply level.
14100
14100
14100
7050
3525
8500
Max
160
160
875
283
—
1.4 V and 1.5 V PCML
Stratix V Device Handbook Volume 1: Overview and Datasheet
8000
4000
2000
2000
Commercial/Industrial
Min
600
100
600
—
30
30
25
chapter.
Speed Grade
650
Typ
—
—
—
—
—
—
—
—
—
—
100
120
150
–2
85
12500
12500
12500
7050
3525
Max
8500
160
160
875
266
—
2000
8000
4000
2000
Commercial/Industrial
Min
600
100
600
—
30
30
25
(Note 1)
Speed Grade
650
Typ
—
—
—
—
—
—
—
—
—
—
100
120
150
–3
85
8500
8500
7050
3525
Max
6500
8500
160
160
875
250
—
2–16
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
Unit
mV
ps
ps



