DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 188

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

5–12
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Slew-Rate Control
I/O Delay
f
f
1
1
The output buffer for each Stratix V device regular- and dual-function I/O pin has a
programmable output slew rate control that you can configure for low-noise or
high-speed performance. A fast slew rate provides high-speed transitions for
high-performance systems. A slow slew rate can help reduce system noise, but adds a
nominal delay to the rising and falling edges. Each I/O pin has an individual slew
rate control, allowing you to specify the slew rate on a pin-by-pin basis.
You cannot use the programmable slew rate feature when using R
The Quartus
and 1—where 0 is slow slew rate and 1 (default) is fast slew rate. Fast slew rates
improve the available timing margin in memory-interface applications or when the
output pin has high-capacitive loading.
Altera recommends performing IBIS or SPICE simulations to determine the best slew
rate setting for your specific application.
The following sections describe programmable IOE delay and programmable output
buffer delay.
Programmable IOE Delay
The Stratix V device IOE includes programmable delays, shown in
page 5–9
increase clock-to-output times. Each pin can have a different input delay from
pin-to-input register or a delay from output register-to-output pin values to ensure
that the bus has the same delay going into or out of the device. This feature helps read
and write timing margins because it minimizes the uncertainties between signals in
the bus.
For more information about programmable IOE delay specifications, refer to the
and Switching Characteristics for Stratix V Devices
Programmable Output Buffer Delay
Stratix V devices support delay chains built inside the single-ended output buffer, as
shown in
rising and falling edge delays of the output buffer, providing the ability to adjust the
output-buffer duty cycle, compensate channel-to-channel skew, reduce simultaneous
switching output (SSO) noise by deliberately introducing channel-to-channel skew,
and improve high-speed memory-interface timing margins. Stratix V devices support
four levels of output buffer delay settings with the default setting of no delay.
For more information about programmable output buffer delay specifications, refer to
the
DC and Switching Characteristics for Stratix V Devices
that you can activate to ensure zero hold times, minimize setup times, or
Figure 5–2 on page
®
II software allows two settings for programmable slew rate control—0
5–9. The delay chains can independently control the
chapter.
Chapter 5: I/O Features in Stratix V Devices
chapter.
May 2011 Altera Corporation
S
Figure 5–2 on
OCT.
I/O Structure
DC