DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 221

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 6: High-Speed Differential I/O Interfaces and DPA in Stratix V Devices
Differential Transmitter
Differential Transmitter
May 2011 Altera Corporation
f
1
For more information about the LVDS transmitter and receiver port list and settings
using ALTLVDS, refer to the
The Stratix V transmitter has dedicated circuitry to provide support for LVDS
signaling. The dedicated circuitry consists of a differential buffer, a serializer, and
fractional PLLs that can be shared between the transmitter and receiver. The
differential buffer can drive out LVDS, mini-LVDS, and RSDS signaling levels. The
serializer takes up to 10 bits wide parallel data from the FPGA fabric, clocks it into the
load registers, and serializes it using shift registers clocked by the fractional PLL
before sending the data to the differential buffer. The MSB of the parallel data is
transmitted first.
When using emulated LVDS I/O standards at the differential transmitter, the SERDES
circuitry must be implemented in logic cells but not hard SERDES.
The load enable (LVDS_LOAD_EN) signal and the diffioclk signal (the clock running at
serial data rate) generated from the fractional PLL clocks the load and shift registers.
You can statically set the serialization factor to x3, x4, x5, x6, x7, x8, x9, or x10 using
the Quartus II software. The load enable signal is derived from the serialization factor
setting.
Figure 6–4. Stratix V Transmitter
Notes to
(1) In SDR and DDR modes, the data width is 1 and 2 bits, respectively.
(2) The tx_in port has a maximum data width of 10 bits.
You can configure any Stratix V transmitter data channel to generate a
source-synchronous transmitter clock output. This flexibility allows the placement of
the output clock near the data outputs to simplify board layout and reduce
clock-to-data skew. Different applications often require specific clock-to-data
alignments or specific data-rate-to-clock-rate factors. The transmitter can output a
clock signal at the same rate as the data with a maximum frequency of 717 MHz. The
output clock can also be divided by a factor of 1, 2, 4, 6, 8, or 10, depending on the
serialization factor. You can set the phase of the clock in relation to the data at 0° or
tx_coreclock
FPGA
Fabric
Figure
Figure 6–4
tx_in 10
6–4:
shows a block diagram of the Stratix V transmitter.
Fractional PLL
DIN
Serializer
3
DOUT
(LVDS_LOAD_EN, diffioclk, tx_coreclock)
ALTLVDS Megafunction User
(Note
2
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
1),
IOE
tx_inclock
(2)
LVDS Transmitter
IOE supports SDR, DDR, or
Non-Registered Datapath
Guide.
LVDS Clock Domain
+
-
tx_out
6–7