DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 373

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off.
and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
SV52002-1.4
Stratix V Device Handbook Volume 3: Transceivers
May 2011
May 2011
SV52002-1.4
f
This chapter provides details about the Stratix
transceiver channels, and a description of the transmitter and receiver channel
datapaths. Stratix V GX and GS devices provide up to 66 backplane capable
full-duplex clock data recovery (CDR)-based transceivers with physical coding
sublayer (PCS) and physical medium attachment (PMA) at serial data rates between
600 Mbps and 12.5 Gbps.
For information about features that will be supported in a future release of the
Quartus
The following sections are included in this chapter:
■
■
■
■
■
Altera
integration, and flexibility. This FPGA family allows you to meet the demands for
increasingly high bandwidth while meeting cost and power budgets.
Stratix V GX devices have columns of transceivers on the left and right sides of the
devices, as shown in
the left side only.
“PMA Architecture” on page 1–5
“Standard PCS Architecture” on page 1–18
“10G PCS Architecture” on page 1–32
“Bonded Configuration” on page 1–42
“PLL Sharing” on page 1–43
®
®
28-nm Stratix V FPGAs deliver the highest bandwidth, levels of system
II software, refer to the
Figure
1–1. Stratix V GS devices have columns of transceivers on
Upcoming Stratix V Device Features
1. Transceiver Architecture in
®
V GX and GS transceiver architecture,
Stratix V Devices
document.
Subscribe