DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 13

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Figure 8. Stratix V Device ALM
The new ALM has the following enhancements:
The Quartus II design software leverages the Stratix V ALM logic structure to deliver the highest
performance, optimal logic utilization and lowest compile times. The Quartus II design software
simplifies design reuse as it automatically maps legacy Stratix designs into the new Stratix V ALM
architecture.
Clocking
The Stratix V device core clock network is designed to support 717 MHz fabric operation and 1066
MHz/2133 Mbps external memory interfaces. The clock network architecture is based on Altera’s proven
global, quadrant and peripheral clock structure which is supported by dedicated clock input pins and
fractional clock synthesis PLLs. All unused sections of the clock network are identified by the Quartus II
design software and powered down to reduce power consumption.
Fractional PLL (fPLL)
Stratix V devices have up to 28 fractional PLLs (fPLLs) that can be used to reduce the number of
oscillators required on a board, as well as reduce clock pins used in the FPGA by synthesizing multiple
clock frequencies from a single reference clock source. Additionally, the fPLLs can be used for clock
network delay compensation, zero-delay buffering and transmit clocking for transceivers. fPLLs may be
individually configured for conventional integer mode, which is equivalent to a general purpose PLL
(GPLL), or enhanced fractional mode with third-order delta-sigma modulation. The fPLLs also support
cascading to and from the transceiver CMU and LC PLLs, thus enabling optical transport muxponder
applications that require precise transmit frequency generation and recovered clock cleanup. Figure 9
shows a typical application.
Altera Corporation



Packs 6% more logic compared to the traditional ALM found in Stratix IV devices
Implements select 7-input LUT-based functions, all 6-input logic functions, and two
independent functions consisting of smaller LUT sizes (such as two independent 4-input LUTs)
to optimize core utilization
Adds more registers (4 registers per 8-input fracturable LUT). This enables Stratix V devices to
maximize core performance at a higher core logic utilization and provides easier timing closure
for register rich and heavily pipelined designs
Stratix V Device Family User Guide Lite
Page 13