DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 16

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

tamper‐protection bit which accepts only encrypted configuration files and easy to use on‐board and off‐
Page 16
Table 7. Stratix V Device Configuration Modes
Automatic Single Event Upset (SEU) Error Detection and Correction
Stratix V devices offer new SEU error detection and correction circuitry that is easy to use and robust. The
correction circuitry includes protection for Configuration RAM (CRAM) programming bits and user
memories. The CRAM is protected by a continuously running CRC error detection circuit with integrated
ECC that automatically corrects one or two errors and detects higher order multi-bit errors. When more
than two errors occur, correction is available through a core programming file reload that provides a
complete design refresh while the FPGA continues to operate.
Furthermore, the physical layout of the FPGA is optimized to make the majority of multi-bit upsets
appear as independent single- or double-bit errors, which are automatically corrected by the integrated
CRAM ECC circuitry. In addition to the CRAM protection in Stratix V devices, the user memories also
include integrated ECC circuitry and are layout optimized to enable error detection of 12-bit errors and
correction for 8-bit errors.
Design Security
Stratix V FPGAs secure designs through industry‐leading anti‐tamper features including an enhanced
AES algorithm in accordance with FIPS‐197, 256‐bit volatile and non‐volatile keys with key bits
scrambled, key bits placed under layers of metal and key bits distributed among other logic, as well as
board key programming.
Altera Corporation
Active Serial
Passive Serial
Passive Parallel
Configuration via PCIe
Partial Reconfiguration
JTAG
Note to Table 7:
(1) Remote update support with Parallel Flash Loader.
Mode
Fast or
Slow
POR



—
—
—
Compression



—
—
—
Encryption





—
Remote
Update
Parallel
Remote
support
Loader.
update
Flash

with


—
—
8, 16, 32
1, 2, 4, 8
Width
Data
1, 4
16
1
1
Stratix V Device Family User Guide Lite
Clock
(MHz)
Rate
Max
100
125
125
125
33
—
Max Data
(Mbps)
3,000
3,000
2,000
Rate
400
125
33