DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 3

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Page 3
The bandwidth growth driven by the mobile Internet affects the wireless infrastructure and causes a fast
upgrade of the entire network infrastructure. The march to 40G/100G systems - with 400G on the near
horizon - is underway. The need for smaller footprints, lower cost and power is accelerating the
introduction of even faster interface technologies like faster transceivers running at 28 Gbps, e.g. for
optical transport and OTU-4. FPGAs are a viable alternative to ASICs and ASSPs for packet processing,
traffic management, switching and routing solutions.
This trend it is not just in the communication space. The conversion from analog to digital television
broadcasting is ongoing and increased bandwidth demands are driven by the proliferation of HD and
1080p worldwide for video production and delivery systems. Military systems require high bandwidth
and higher performance, higher precision DSP performance, system reliability and design security to
meet the requirements in secure communication, electronic warfare and embedded computing
applications. In computer and storage, main drivers are the growth of traffic and data processing at lower
latency. Applications like cloud computing drive up bandwidth dramatically but power consumption
affects the total cost of ownership.
Stratix V FPGAs – Built for Bandwidth
FPGAs are the platform of choice when it comes to flexibility. With increased integration through
extensive hardening of functions, Stratix V FPGAs provides the ultimate flexibility. This is enabled by
partial reconfiguration of the FPGA core, as well as dynamic reconfiguration of the transceivers. With
partial reconfiguration, you can increase your system functionality dramatically and achieve faster
reconfiguration while also reducing power.
Following are brief summaries of the key new innovations that enable the highest bandwidth and
integration in your system, while achieving a 50% increased system performance and lowering the total
power by 30% compared to the previous generation Stratix IV FPGAs.
Embedded HardCopy Blocks
Embedded HardCopy Blocks (EHB) are customizable hard intellectual property (IP) blocks that leverage
Altera’s unique HardCopy ASIC capabilities. This innovation substantially increases FPGA capabilities
by dramatically increasing density per area and offering up to 14M ASIC gates or up to 700K logic
elements. There are significant performance and power benefits ‐ 2X the performance at up to 65% ‐ lower
power by using the hard IP rather than soft logic.
The difference to a traditional use of hard IP is the HardCopy methodology which allows customers to
take advantage of product variants or implement their custom functions quickly and efficiently without
the mask and development cost‐associated with a full chip design.
The EHB Blocks harden standard or logic‐intensive functions such as application‐specific functions,
transceiver protocols and proprietary customer IP functions. This offers customers faster time to market
for their designs, higher bandwidth and performance while reducing cost and power. For Altera, this
innovation allows the company to quickly – usually less than 3‐6 months ‐ create variant products for
target applications.
Altera Corporation
Stratix V Device Family User Guide Lite