DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 6

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Page 6
Figure 4. Industry’s First Variable-Precision DSP Block - Set the Precision Dial to Match your Application
Stratix V FPGAs feature the industry's first variable precision DSP block that can be configured to
natively support signal processing with precision ranging from 9×9 all the way up to 54×54. The DSP
blocks are designed to be cascaded with the widest, dedicated cascade bus in the industry – 64 bits. This
allows the building of DSP data paths of even higher precision in the most efficient manner with
maximum performance.
The variable precision DSP block is designed to enable the most silicon efficient implementation of your
signal processing chain. It is the industry’s only DSP block architecture to feature a configurable 18/26
pre-adder, a 64-bit accumulator + cascade bus and an internal co-efficient storage – all designed to allow
the most area efficient implementation of common functions such as FIR filters, FFTs and floating point.
While this block is backward compatible with all the existing modes supported by our 65-nm and 40-nm
devices, it adds native, efficient support for a range of higher precision modes.
Each DSP block can be independently configured at compile time as either dual 18×18 or a single 27×27
multiply accumulate. With a dedicated 64-bit cascade bus, multiple variable precision DSP blocks can be
cascaded to implement even higher precision DSP functions efficiently. Table 5 shows how different
precision is accommodated within a DSP block or by utilizing multiple blocks.
Table 1. Variable Precision DSP Block Configurations
Complex multiplication is very common in DSP algorithms. One of the most popular applications of
complex multipliers is the FFT algorithm. This algorithm has the characteristic of increasing precision
requirements on only one side of the multiplier. The variable precision DSP block is designed to support
this with proportional increase in DSP resources with precision growth.
Altera Corporation
Multiplier
18×18 bit
27×27 bit
36×36 bit
54×54 bit
9×9 bit
Size
1/3 of Variable Precision DSP Block
1/2 of Variable Precision DSP Block
2 Variable Precision DSP Blocks
4 Variable Precision DSP Blocks
1 Variable Precision DSP Block
DSP Block Resources
High precision fixed or single precision floating point
Very high precision fixed point
Double precision floating point
Medium precision fixed point
Low precision fixed point
Expected Usage
Stratix V Device Family User Guide Lite