DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 4

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DK-DEV-5SGXEA7/ES

Manufacturer Part Number
DK-DEV-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Datasheets

Specifications of DK-DEV-5SGXEA7/ES

Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2725
Page 4
Figure 2. Altera’s new Embedded HardCopy Block in Stratix V FPGAs
PCI Express Gen 3/2/1 Hard IP (EHB)
The Stratix V devices have PCI Express hard IP designed for performance, ease-of-use and increased
functionality. The PCI Express hard IP consists of the PCS, Data Link and Transaction layers. The PCI
Express hard IP supports Gen 3/2/1 End Point and Root Port up to a ×8 lane configuration. The Stratix V
PCI Express hard IP operates independently from the core logic which enables the PCI Express link to
wake up and complete link training in less than 100 ms, while the Stratix V device completes loading the
programming file for the rest of the FPGA. It also provides added functionality, making it easier to
support emerging features such as Single Root IO Virtualization (SR-IOV) or optional protocol
extensions. In addition, the Stratix V device PCI Express hard IP has improved end-to-end data path
protection using Error Checking and Correction (ECC) and now supports Configuration via PCI Express.
See detailed description in the
Stratix V Device
Handbook.
40G and 100G Ethernet Hard IP (EHB)
The 40G and 100G Ethernet hard IP in Stratix V GT and Stratix V GX devices is standards- compliant and
proven. The Hard IP includes 40GBASE-R PCS and XLAUI PMA for 40GE, and 100GBASE-R PCS and
CAUI PMA for 100GE. The 40G and 100G Ethernet hard IP are scalable because applications requiring
multiple 40/100 GbE ports may use a single PLL for the 40/100GBASE-R PCS instantiations to reduce
FPGA core and clock resources.
Furthermore, the integrated 10G transceiver simplifies multi-port 40/100GbE systems implementation by
reducing chip count, board space, and power. Stratix V transceivers interface directly with 40Gbps QSFP
and SFP, and 100 Gbps CFP pluggable modules.
Altera Corporation
Stratix V Device Family User Guide Lite

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