DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 8

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Page 8
Figure 5. Partial Reconfiguration for the FPGA Core
Partial reconfiguration is supported through the following configuration options:
Dynamic reconfiguration on the other hand enables data rates or encoding schemes to be changed
dynamically while maintaining data transfer on adjacent transceiver channels in Stratix V GT/GX/GS
devices. Dynamic reconfiguration is ideal for applications requiring on-the-fly multi-protocol or multi-
rate support. The PMA and PCS blocks can be reconfigured with dynamic reconfiguration, thus
providing the ultimate flexibility which in turn enables differentiation.
Partial reconfiguration can be seamlessly used in tandem with dynamic reconfiguration to enable partial
reconfiguration of both core and I/O simultaneously. Application operation is not affected during
reconfiguration, there is no system downtime with dynamic updates, thus allowing faster reconfiguration
and reducing cost and power through integration.
Embedded Low Power Serial Transceivers
Stratix V FPGAs deliver the industry’s most flexible transceivers with the highest bandwidth from 600
Mbps to 28 Gbps, low Bit Error Ratio (BER), and low power. Many enhancements have been made to the
Stratix V transceivers, which improve flexibility and robustness. These enhancements include:
In addition, all transceivers are identical with full-featured embedded PCS hard IP to simplify the design,
lower the power and save valuable core resources. Stratix V transceivers are designed to be standard-
compliant for a wide range of
conditioning features to support backplane, optical module and chip-to-chip applications.
The transceivers are positioned on the outer edges of the chip as shown in Figure 6. They are isolated
from the rest of the chip to prevent core and I/O noise from coupling into the transceivers; thereby
ensuring optimal signal integrity. The transceiver channels consist of the Physical Medium Attachment
Altera Corporation








Low jitter LC (inductor-capacitor) Transmit PLLs
Robust analog receive Clock and Data Recovery (CDR)
Advanced pre-emphasis and equalization for 14.1 Gbps backplanes
28 Gbps chip-to-chip transceivers (Stratix V GT)
On-chip instrumentation
Partial reconfiguration through the FPP ×16 I/O interface
Configuration via PCI Express
Soft internal core such as the Nios
protocols
and data rates, and are equipped with a variety of signal
®
II embedded processor
Stratix V Device Family User Guide Lite