DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 9

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

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(PMA), Physical Coding Sub-layer (PCS), ultralow jitter LC transmit PLLs and clock networks. Unused
transceiver PMA channels can also be used as additional transmit PLLs. Reference clocks for the
transceivers are either derived from off-chip oscillators, or generated on-chip with the precise frequency
synthesis capabilities of the fPLLs (see Page 11 for detailed description). fPLLs synthesize multiple clock
frequencies from a single reference clock source and replace multiple reference oscillators in multi-
protocol or multi-rate applications.
The Stratix V core logic connects to the PCS through an 8, 10, 16, 20, 32, 40, 64 or 66-bit interface,
depending on the transceiver data rate and protocol. Stratix V devices contain PCS hard IP to support PCI
Express Gen 3/2/1, 40G/100G Ethernet, Interlaken, 10GE, XAUI, GbE, SRIO, CPRI and GPON (see Table
3 for PMA features). All other standard and proprietary protocols from 600 Mbps to 14.1 Gbps are
supported through the 10G Basic (up to 14.1 Gbps), 6G Basic (up to 8.5 Gbps) and 3G Basic (up to 3.75
Gbps) transceiver PCS hard IP. Table 4 lists the transceiver PCS features.
Notes to Figure 6:
(1) This figure represents a given variant of a Stratix V device with transceivers. Other variants may have a different floorplan than the one shown here.
(2) You can use the unused transceiver channels as additional transceiver transmit PLLs.
Figure 6. Stratix V GT/GX/GST Device Chip View
Altera Corporation
Stratix V Device Family User Guide Lite