DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 7

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Table 2. Complex Multiplication with Variable Precision DSP Blocks
Additionally, for FFT applications with high dynamic range requirements, only the Altera FFT Megacore
offers an option of single precision floating point implementation, with resource usage and performance
similar to high precision fixed point implementations.
Other new features include:
The variable precision DSP block is ideal to support the growing trend towards higher bit precision in
high performance DSP applications. At the same time, it can efficiently support the many existing 18-bit
DSP applications, such as high definition video processing and remote radio heads. The Stratix V FPGA
series, with the variable precision DSP block architecture, is the only FPGA family that can efficiently
support many different precision levels, up to and including floating point implementations. This
flexibility results in increased system performance, reduced power consumption and reduced
architecture constraints on system algorithm designers.
Easy-to-Use Partial Reconfiguration
Partial reconfiguration allows designers to reconfigure designated sections of the FPGA while other
sections remain running. This is required in systems where uptime is critical. It allows customers to make
updates or adjust functionality without disrupting device operation, while lowering power and cost.
Partial reconfiguration also increases the effective logic density by removing the necessity to place FPGA
functions that do not operate simultaneously. Instead, these functions can be stored in external memory
and loaded as required. This reduces the size of the FPGA by allowing multiple applications on a single
FPGA, saving board space and reducing power.
Partial reconfiguration solutions typically have been time-intensive tasks that required designers to know
the majority of the intricate FPGA architecture details. Altera has simplified the partial reconfiguration
process by building the capability on top of a proven methodology using LogicLock
compile design flow in its Quartus II design software.
Altera Corporation
Multiplier
18×18 bits
18×25 bits
18×36 bits
27×27 bits







Size
64-bit accumulator, the largest in the industry
Hard Pre-adder, available in both 18 and 27 bit modes
Cascaded output adders, for efficient systolic FIR filters
Internal coefficient register banks
Enhanced independent multiplier operation
Efficient support for single and double precision floating point arithmetic
Inferability of all modes by the Quartus II design suite
2 Variable Precision DSP Blocks
3 Variable Precision DSP Blocks
4 Variable Precision DSP Blocks
4 Variable Precision DSP Blocks
DSP Block Resources
Accommodate bit growth through FFT stages
Highest precision FFT stages
Single precision floating point
Expected Usage
Resource optimized FFTs
Stratix V Device Family User Guide Lite
™
and incremental
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