DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 2

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

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DSP blocks, and fractional clock synthesis PLLs (fPLLs), interconnected by Altera’s multi-track routing
architecture and comprehensive fabric clocking network.
Also common to Stratix V family variants is the new Embedded HardCopy Block (EHB) which is a
customizable hard IP block that leverages Altera’s unique HardCopy ASIC capabilities. The EHB is used
for hardening standard or logic intensive functions such as interface protocols, application-specific
functions and proprietary custom IP. Hardening IP into the EHB frees up valuable core logic resources
and reduces overall system power and cost. The EHB blocks in Stratix V include hard IP instantiations of
PCI Express Gen3/2/1 and 40GbE/100GbE. This innovation enables Altera to respond faster to customer
requirements by hardening other IP into the EHB for future product variants.
Stratix V Family Plan
Tables 1-1, 1-2, 1-3, and 1-4 on pages 6-11 of the
Stratix V Device Handbook
show the Stratix V
GT/GX/GS/E device features.
Moving to HardCopy V Devices
HardCopy V ASICs offer the lowest risk and lowest total cost in ASIC designs with embedded high speed
transceivers. You can prototype and debug with Stratix V FPGAs, then use HardCopy V ASICs for
volume production. The proven turnkey process creates a functionally-equivalent HardCopy V ASIC
with or without embedded transceivers to meet all timing constraints in as little as 12 weeks.
The powerful combination of Stratix V FPGAs and HardCopy V ASICs can help meet your design
requirements. Whether you are planning for ASIC production and require the lowest risk, lowest cost
path from specification to production or require a cost reduction path for your FPGA-based systems,
Altera provides the optimal solution for power, performance, and device bandwidth.
Market Dynamics for High-End Systems
The challenges of increased bandwidth with fixed cost and power budgets are not only being driven by
applications like mobile internet and video in communication markets but across many other market
segments and applications. The innovations available in the 28-nm Stratix V FPGA family dramatically
improve the density and I/O performance of Altera’s FPGAs and HardCopy ASICs. With these
innovations we address the challenges in a way that takes the industry beyond the benefits of Moore’s
Law and further strengthens our competitive position vs. ASICs and ASSPs.
Figure 1. Multi-Market Demand for Higher Bandwidth in the Same Footprint with the Same or Lower Power and Cost
Altera Corporation
Stratix V Device Family User Guide Lite