LPC2361_62 NXP Semiconductors, LPC2361_62 Datasheet - Page 12

• Manufacturer Part Number: LPC2361_62
• Description: The LPC2361/2362 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation that combines the microcontroller with up to 128 kB of embedded high-speed flash memory
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 3.
[1]
[2]
LPC2361_62
Product data sheet
Symbol
P4[28]/MAT2[0]/
TXD3
P4[29]/MAT2[1]/
RXD3
TDO
TDI
TMS
TRST
TCK
RTCK
RSTOUT
RESET
XTAL1
XTAL2
RTCX1
RTCX2
V
V
V
V
V
VREF
VBAT
SS
SSA
DD(3V3)
DD(DCDC)(3V3)
DDA
5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.
5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a DAC input,
digital section of the pad is disabled.
Pin description
Pin
82
85
1
2
3
4
5
100
14
17
22
23
16
18
15, 31,
41, 55,
72, 97,
83
11
28, 54,
71,
96
13, 42,
84
10
12
19
[1][7]
[1][8]
[1][8]
[1][8]
[1][7]
[14]
[1]
[1]
[9]
[10][11]
[10][11]
[10][12]
[10][12]
[13]
[15]
[16]
[17]
[17]
[17]
[1][8]
…continued
Type
I/O
O
O
I/O
O
I
O
I
I
I
I
I/O
O
I
I
O
I
O
I
I
I
I
I
I
I
Description
P4[28] — General purpose digital input/output pin.
MAT2[0] — Match output for Timer 2, channel 0.
TXD3 — Transmitter output for UART3.
P4[29] — General purpose digital input/output pin.
MAT2[1] — Match output for Timer 2, channel 1.
RXD3 — Receiver input for UART3.
TDO — Test Data out for JTAG interface.
TDI — Test Data in for JTAG interface.
TMS — Test Mode Select for JTAG interface.
TRST — Test Reset for JTAG interface.
TCK — Test Clock for JTAG interface. This clock must be slower than
CPU clock (CCLK) for the JTAG interface to operate
RTCK — JTAG interface control signal.
Note: LOW on this pin while RESET is LOW enables ETM pins (P2[9:0]) to
operate as trace port after reset.
RSTOUT — This is a 3.3 V pin. LOW on this pin indicates LPC2361/2362 being in
Reset state.
External reset input: A LOW on this pin resets the device, causing I/O ports and
peripherals to take on their default states, and processor execution to begin at
address 0. TTL with hysteresis, 5 V tolerant.
Input to the oscillator circuit and internal clock generator circuits.
Output from the oscillator amplifier.
Input to the RTC oscillator circuit.
Output from the RTC oscillator circuit.
ground: 0 V reference.
analog ground: 0 V reference. This should nominally be the same voltage as
V
3.3 V supply voltage: This is the power supply voltage for the I/O ports.
3.3 V DC-to-DC converter supply voltage: This is the supply voltage for the
on-chip DC-to-DC converter only.
analog 3.3 V pad supply voltage: This should be nominally the same voltage as
V
power the ADC and DAC.
ADC reference: This should be nominally the same voltage as V
should be isolated to minimize noise and error. Level on this pin is used as a
reference for ADC and DAC.
RTC power supply: 3.3 V on this pin supplies the power to the RTC peripheral.
All information provided in this document is subject to legal disclaimers.
SS
DD(3V3)
, but should be isolated to minimize noise and error.
Rev. 5 — 25 October 2011
but should be isolated to minimize noise and error. This voltage is used to
Single-chip 16-bit/32-bit MCU
LPC2361/62
© NXP B.V. 2011. All rights reserved.
DD(3V3)
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