LPC2361_62 NXP Semiconductors, LPC2361_62 Datasheet - Page 32

• Manufacturer Part Number: LPC2361_62
• Description: The LPC2361/2362 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation that combines the microcontroller with up to 128 kB of embedded high-speed flash memory
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2361_62
Product data sheet
7.24.5 External interrupt inputs
7.24.6 Memory mapping control
7.25.1 EmbeddedICE
7.25.2 Embedded trace
7.25 Emulation and debugging
The second AHB, referred to as AHB2, includes only the Ethernet block and an
associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary
AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into
unused space in memory residing on AHB1.
In summary, bus masters with access to AHB1 are the ARM7 itself, the USB block, the
GPDMA function, and the Ethernet block (via the bus bridge from AHB2). Bus masters
with access to AHB2 are the ARM7 and the Ethernet block.
The LPC2361/2362 include up to 46 edge sensitive interrupt inputs combined with up to
four level sensitive external interrupt inputs as selectable pin functions. The external
interrupt inputs can optionally be used to wake up the processor from Power-down mode.
The memory mapping control alters the mapping of the interrupt vectors that appear at the
beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the Boot
ROM or the SRAM. This allows code running in different memory spaces to have control
of the interrupts.
The LPC2361/2362 support emulation and debugging via a JTAG serial port. A trace port
allows tracing program execution. Debugging and trace functions are multiplexed only
with GPIOs on P2[0] to P2[9]. This means that all communication, timer, and interface
peripherals residing on other pins are available during the development and debugging
phase as they are when the application is run in the embedded system itself.
The EmbeddedICE logic provides on-chip debug support. The debugging of the target
system requires a host computer running the debugger software and an EmbeddedICE
protocol convertor. The EmbeddedICE protocol convertor converts the Remote Debug
Protocol commands to the JTAG data needed to access the ARM7TDMI-S core present
on the target system.
The ARM core has a Debug Communication Channel (DCC) function built-in. The DCC
allows a program running on the target to communicate with the host debugger or another
separate host without stopping the program flow or even entering the debug state. The
DCC is accessed as a co-processor 14 by the program running on the ARM7TDMI-S
core. The DCC allows the JTAG port to be used for sending and receiving data without
affecting the normal program flow. The DCC data and control registers are mapped in to
addresses in the EmbeddedICE logic.
The JTAG clock (TCK) must be slower than
interface to operate.
Since the LPC2361/2362 have significant amounts of on-chip memories, it is not possible
to determine how the processor core is operating simply by observing the external pins.
The ETM provides real-time trace capability for deeply embedded processor cores. It
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 25 October 2011
1
⁄
6
of the CPU clock (CCLK) for the JTAG
Single-chip 16-bit/32-bit MCU
LPC2361/62
© NXP B.V. 2011. All rights reserved.
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