LPC2361_62 NXP Semiconductors, LPC2361_62 Datasheet - Page 20

• Manufacturer Part Number: LPC2361_62
• Description: The LPC2361/2362 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation that combines the microcontroller with up to 128 kB of embedded high-speed flash memory
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2361_62
Product data sheet
7.10.2.1 Features
7.10.3.1 Features
7.10.2 USB host controller
7.10.3 USB OTG controller
7.11 CAN controller and acceptance filters
The host controller enables full- and low-speed data exchange with USB devices attached
to the bus. It consists of register interface, serial interface engine, and DMA controller. The
register interface complies with the OHCI specification.
USB OTG (On-The-Go) is a supplement to the USB 2.0 specification that augments the
capability of existing mobile devices and USB peripherals by adding host functionality for
connection to USB peripherals.
The OTG Controller integrates the Host Controller, device controller, and a master-only
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controls an external OTG transceiver.
The Controller Area Network (CAN) is a serial communications protocol which efficiently
supports distributed real-time control with a very high level of security. Its domain of
application ranges from high-speed networks to low cost multiplex wiring.
The CAN block is intended to support multiple CAN buses simultaneously, allowing the
device to be used as a gateway, switch, or router among a number of CAN buses in
industrial or automotive applications.
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C interface to implement OTG dual-role device functionality. The dedicated I
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Scalable realization of endpoints at run time.
Endpoint Maximum packet size selection (up to USB maximum specification) by
software at run time.
Supports SoftConnect and GoodLink features.
While the USB is in the Suspend mode, the LPC2361/2362 can enter one of the
reduced power modes and wake up on USB activity.
Supports DMA transfers with the DMA RAM of 16 kB on all non-control endpoints.
Allows dynamic switching between CPU-controlled and DMA modes.
Double buffer implementation for Bulk and Isochronous endpoints.
OHCI compliant.
Two downstream ports.
Supports per-port power switching.
Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision
1.0a.
Hardware support for Host Negotiation Protocol (HNP).
Includes a programmable timer required for HNP and Session Request Protocol
(SRP).
Supports any OTG transceiver compliant with the OTG Transceiver Specification
(CEA-2011), Rev. 1.0.
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 25 October 2011
Single-chip 16-bit/32-bit MCU
LPC2361/62
© NXP B.V. 2011. All rights reserved.
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C interface
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