MC68HC711E20CFS2 MOTOROLA [Motorola, Inc], MC68HC711E20CFS2 Datasheet - Page 162

• Manufacturer Part Number: MC68HC711E20CFS2
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Timing System
9.7.2 Pulse Accumulator Count Register
9.7.3 Pulse Accumulator Status and Interrupt Bits
Data Sheet
162
DDRA3 — Data Direction for Port A Bit 3
I4/O5 — Input Capture 4/Output Compare 5 Bit
RTR[1:0] — RTI Interrupt Rate Select Bits
This 8-bit read/write register contains the count of external input events at the PAI
input or the accumulated count. The PACNT is readable even if PAI is not active in
gated time accumulation mode. The counter is not affected by reset and can be
read or written at any time. Counting is synchronized to the internal PH2 clock so
that incrementing and reading occur during opposite half cycles.
The pulse accumulator control bits, PAOVI and PAII, PAOVF and PAIF, are located
within timer registers TMSK2 and TFLG2.
Refer to
Refer to
Address:
Address:
Address:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
0 = Output compare 5 function enable (no IC4)
1 = Input capture 4 function enable (no OC5)
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 9-26. Pulse Accumulator Count Register (PACNT)
Section 6. Parallel Input/Output (I/O)
9.5 Real-Time Interrupt
$1027
$1024
$1025
Bit 7
Figure 9-27. Timer Interrupt Mask 2 Register (TMSK2)
Bit 7
Bit 7
Bit 7
TOF
TOI
Figure 9-28. Timer Interrupt Flag 2 Register (TFLG2)
0
0
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= Unimplemented
= Unimplemented
Bit 6
RTIF
RTII
6
6
0
6
0
Timing System
PAOVF
PAOVI
Bit 5
5
5
0
5
0
Indeterminate after reset
(RTI).
Bit 4
PAIF
PAII
4
4
0
4
0
Bit 3
3
3
0
3
0
Ports.
Bit 2
M68HC11E Family — Rev. 5
2
2
0
2
0
Bit 1
PR1
1
1
0
1
0
MOTOROLA
Bit 0
Bit 0
Bit 0
Bit 0
PR0
0
0