MC68HC711E20CFS2 MOTOROLA [Motorola, Inc], MC68HC711E20CFS2 Datasheet - Page 73
MC68HC711E20CFS2
Manufacturer Part Number
MC68HC711E20CFS2
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC711E20CFS2.pdf
(268 pages)
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4.1 Introduction
4.2 CPU Registers
M68HC11E Family — Rev. 5
MOTOROLA
Data Sheet — M68HC11E Family
Features of the M68HC11 Family include:
The CPU is designed to treat all peripheral, input/output (I/O), and memory
locations identically as addresses in the 64-Kbyte memory map. This is referred to
as memory-mapped I/O. There are no special instructions for I/O that are separate
from those used for memory. This architecture also allows accessing an operand
from an external memory location with no execution time penalty.
M68HC11 CPU registers are an integral part of the CPU and are not addressed as
if they were memory locations. The seven registers, discussed in the following
paragraphs, are shown in
•
•
•
•
•
Central processor unit (CPU) architecture
Data types
Addressing modes
Instruction set
Special operations such as subroutine calls and interrupts
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Central Processor Unit (CPU)
Section 4. Central Processor Unit (CPU)
Figure
4-1.
Data Sheet
73
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