MC68HC711E20CFS2 MOTOROLA [Motorola, Inc], MC68HC711E20CFS2 Datasheet - Page 87

MC68HC711E20CFS2

Manufacturer Part Number

MC68HC711E20CFS2

Description

Microcontrollers

Manufacturer

MOTOROLA [Motorola, Inc]

Datasheet

1.MC68HC711E20CFS2.pdf (268 pages)

Current page: 87 of 268
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M68HC11E Family — Rev. 5

MOTOROLA

Cycle

Operands

Operators

( )

⇐

⇑

⇓

•

⊕

∗

–

Mnemonic

TST (opr)

XGDX

XGDY

TEST

TSTA

TSTB

SWI

TAB

TAP

TBA

TPA

TSX

TSY

TXS

TYS

WAI

Infinity or until reset occurs

12 cycles are used beginning with the opcode fetch. A wait state is entered which remains in effect for an integer number of MPU E-clock

cycles (n) until an interrupt is recognized. Finally, two additional cycles are used to fetch the appropriate interrupt vector (14 + n total).

= 8-bit direct address ($0000–$00FF) (high byte assumed to be $00)

= 8-bit positive offset $00 (0) to $FF (255) (is added to index)

= High-order byte of 16-bit extended address

= One byte of immediate data

= High-order byte of 16-bit immediate data

= Low-order byte of 16-bit immediate data

= Low-order byte of 16-bit extended address

= 8-bit mask (set bits to be affected)

= Signed relative offset $80 (–128) to $7F (+127)

Contents of register shown inside parentheses

Is transferred to

Is pulled from stack

Is pushed onto stack

Boolean AND

Arithmetic addition symbol except where used as inclusive-OR symbol

in Boolean formula

Exclusive-OR

Multiply

Concatenation

Arithmetic subtraction symbol or negation symbol (two’s complement)

(offset relative to address following machine code offset byte))

Test for Zero or

Transfer A to B

Transfer B to A

Test A for Zero

Test B for Zero

Transfer Stack

TEST (Only in

Stack Pointer

Transfer A to

Transfer X to

Transfer Y to

Test Modes)

CC Register

Transfer CC

Exchange D

Pointer to X

Pointer to Y

Operation

Software

or Minus

Interrupt

Wait for

with X

with Y

Minus

Address Bus Counts

Stack Regs & WAIT

IX ⇒ D, D ⇒ IX

IY ⇒ D, D ⇒ IY

See Figure 3–2

Description

SP + 1 ⇒ IX

SP + 1 ⇒ IY

IX – 1 ⇒ SP

IY – 1 ⇒ SP

A ⇒ CCR

CCR ⇒ A

A ⇒ B

B ⇒ A

M – 0

A – 0

B – 0

Table 4-2. Instruction Set (Sheet 7 of 7)

Freescale Semiconductor, Inc.

For More Information On This Product,

Addressing

Go to: www.freescale.com

Central Processor Unit (CPU)

Mode

INH

EXT

IND,X

IND,Y

INH

Opcode

Instruction

Condition Codes

—

∆

↓

Operand

—

Bit not changed

Bit always cleared

Bit always set

Bit cleared or set, depending on operation

Bit can be cleared, cannot become set

Cycles

—

∆

Central Processor Unit (CPU)

—

↓

—

∆

Condition Codes

—

∆

—

∆

Instruction Set

—

∆

Data Sheet

—

∆

—

∆

MC68HC711E20CFS2 MOTOROLA [Motorola, Inc], MC68HC711E20CFS2 Datasheet - Page 87

MC68HC711E20CFS2

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