HD6417615AF60 HITACHI [Hitachi Semiconductor], HD6417615AF60 Datasheet - Page 12

• Manufacturer Part Number: HD6417615AF60
• Description: CMOS single-chip microcontroller
• Manufacturer: HITACHI [Hitachi Semiconductor]

10.3 Operation............................................................................................................................ 441
Section 11 Direct Memory Access Controller (DMAC)
11.1 Overview............................................................................................................................ 453
11.2 Register Descriptions ......................................................................................................... 458
11.3 Operation............................................................................................................................ 469
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10.2.1 E-DMAC Mode Register (EDMR)....................................................................... 415
10.2.2 E-DMAC Transmit Request Register (EDTRR) .................................................. 416
10.2.3 E-DMAC Receive Request Register (EDRRR).................................................... 417
10.2.4 Tx Descriptor List Address Register (TDLAR).................................................... 418
10.2.5 Rx Descriptor List Address Register (RDLAR) ................................................... 419
10.2.6 EtherC/E-DMAC Status Register (EESR)............................................................ 420
10.2.7 EtherC/E-DMAC Status Interrupt Permission Register (EESIPR) ...................... 425
10.2.8 Tx/Rx Status Copy Enable Register (TRSCER) .................................................. 430
10.2.9 Receive Missed-Frame Counter Register (RMFCR)............................................ 431
10.2.10 Tx FIFO Threshold Register (TFTR) ................................................................... 432
10.2.11 FIFO Depth Register (FDR) ................................................................................. 434
10.2.12 Receiver Control Register (RCR) ......................................................................... 435
10.2.13 E-DMAC Operation Control Register (EDOCR) ................................................. 436
10.2.14 Receiving-Buffer Write Address Register (RBWAR).......................................... 437
10.2.15 Receiving-Descriptor Fetch Address Register (RDFAR)..................................... 438
10.2.16 Transmission-Buffer Read Address Register (TBRAR) ...................................... 439
10.2.17 Transmission-Descriptor Fetch Address Register (TDFAR)................................ 440
10.3.1 Descriptor List and Data Buffers.......................................................................... 441
10.3.2 Transmission ......................................................................................................... 447
10.3.3 Reception .............................................................................................................. 449
10.3.4 Multi-Buffer Frame Transmit/Receive Processing............................................... 451
11.1.1 Features ................................................................................................................. 453
11.1.2 Block Diagram...................................................................................................... 455
11.1.3 Pin Configuration.................................................................................................. 456
11.1.4 Register Configuration.......................................................................................... 457
11.2.1 DMA Source Address Registers 0 and 1 (SAR0, SAR1) ..................................... 458
11.2.2 DMA Destination Address Registers 0 and 1 (DAR0, DAR1) ............................ 458
11.2.3 DMA Transfer Count Registers 0 and 1 (TCR0, TCR1)...................................... 459
11.2.4 DMA Channel Control Registers 0 and 1 (CHCR0, CHCR1).............................. 460
11.2.5 DMA Vector Number Registers 0 and 1 (VCRDMA0, VCRDMA1).................. 464
11.2.6 DMA Request/Response Selection Control Registers 0 and 1
11.2.7 DMA Operation Register (DMAOR) ................................................................... 467
11.3.1 DMA Transfer Flow ............................................................................................. 469
11.3.2 DMA Transfer Requests ....................................................................................... 471
11.3.3 Channel Priorities.................................................................................................. 475
11.3.4 DMA Transfer Types............................................................................................ 478
(DRCR0, DRCR1)................................................................................................ 465
.......................................... 453