HD6417615AF60 HITACHI [Hitachi Semiconductor], HD6417615AF60 Datasheet - Page 778

• Manufacturer Part Number: HD6417615AF60
• Description: CMOS single-chip microcontroller
• Manufacturer: HITACHI [Hitachi Semiconductor]

20.4.4
When the clock is input from the CKIO pin, the clock frequency can be modified or the clock
stopped. The CKPREQ/CKM pin is provided for this purpose. Note that clock pauses are not
accepted while the watchdog timer (WDT) is operating (i.e. when the timer enable bit (TME) in
the WDT’s timer control/status register (WTCSR) is 1). When the clock pause request function is
used, the standby bit (SBY) in the standby control register 1 (SBYCR1) must be set to 1 before
inputting the request signal. The clock pause function is used as described below.
1. Set the TME bit in the watchdog timer’s WTCSR register to 0, and set the SBY bit in SBYCR1
2. Apply a low level to the CKPREQ/CKM pin.
3. When the chip enters the standby state internally, a low level is output from the CKPACK pin.
4. After confirming that the CKPACK pin has gone low, perform clock halting or frequency
5. To cancel the clock pause state (standby state), apply a high level to the CKPREQ/CKM pin.
768
Oscillator
(output)
to 1.
modification.
(Inside the chip , the standby state is canceled by detecting a rising edge at the CKPREQ/CKM
pin.)
NMIE
CKIO
SBY
NMI
Clock Pause Function
Figure 20.1 Standby Mode Cancellation by NMI Interrupt
exception
handling
NMI
SLEEP instruction
service routine,
Exception
SBY = 1,
Standby mode
oscillation
Start of
settling time
Oscillation
set time
WDT
NMI exception
handling