HD6417615AF60 HITACHI [Hitachi Semiconductor], HD6417615AF60 Datasheet - Page 153

• Manufacturer Part Number: HD6417615AF60
• Description: CMOS single-chip microcontroller
• Manufacturer: HITACHI [Hitachi Semiconductor]

4.5
4.5.1
Exception handling can be triggered by a trap instruction, general illegal instruction or illegal slot
instruction, as shown in table 4.9.
Table 4.9
Type
Trap instruction
Illegal slot
instruction
General illegal
instruction
4.5.2
When a TRAPA instruction is executed, trap instruction exception handling starts. The CPU
operates as follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
3. The exception service routine start address is fetched from the exception vector table entry that
instruction to be executed after the TRAPA instruction.
corresponds to the vector number specified by the TRAPA instruction. That address is jumped
to and the program starts executing. The jump that occurs is not a delayed branch.
Exceptions Triggered by Instructions
Instruction-Triggered Exception Types
Trap Instructions
Types of Exceptions Triggered by Instructions
Source Instruction
TRAPA
Undefined code placed
immediately after a delayed
branch instruction (delay slot)
and instructions that rewrite the
PC
Undefined code anywhere
besides in a delay slot
Comment
—
Delayed branch instructions: JMP, JSR,
BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
Instructions that rewrite the PC: JMP, JSR,
BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF
—
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