HD6417615AF60 HITACHI [Hitachi Semiconductor], HD6417615AF60 Datasheet - Page 567
HD6417615AF60
Manufacturer Part Number
HD6417615AF60
Description
CMOS single-chip microcontroller
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
1.HD6417615AF60.pdf
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The serial mode register (SCSMR) is an 8-bit register used to set the SCIF’s serial communication
format and select the baud rate generator clock source. In IrDA communication mode, it is used to
select the output pulse width.
SCSMR can be read or written to by the CPU at all times.
SCSMR is initialized to H'00 by a reset, by the module standby function, and in standby mode.
Bit 7—Communication Mode (C/A): Selects asynchronous mode or synchronous mode as the
SCIF operating mode. In IrDA communication mode, this bit must be cleared to 0.
Bit 7: C/A
0
1
Bit 6—Character Length (CHR)/IrDA Clock Select 3 (ICK3): Selects 7 or 8 bits as the data length
in asynchronous mode. In synchronous mode, a fixed data length of 8 bits is used regardless of the
CHR setting,
Bit 6: CHR
0
1
Note: * When 7-bit data is selected, the MSB (bit 7) of the transmit FIFO data register (SCFTDR) is
In IrDA communication mode, bit 6 is the IrDA clock select 3 (ICK3) bit, enabling appropriate
clock pulses to be generated according to its setting. See Pulse Width Selection, in section 14.3.6,
Operation in IrDA Mode, for details.
Bit 5—Parity Enable (PE)/IrDA Clock Select 2 (ICK2): In asynchronous mode, selects whether or
not parity bit addition is performed in transmission, and parity bit checking in reception. In
synchronous mode, parity bit addition and checking is not performed, regardless of the PE bit
setting.
Bit 5: PE
0
1
Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to
554
not transmitted.
transmit data before transmission. In reception, the parity bit is checked for the parity (even
or odd) specified by the O/E bit.
Description
Asynchronous mode
Synchronous mode
Description
8-bit data
7-bit data*
Description
Parity bit addition and checking disabled
Parity bit addition and checking enabled*
(Initial value)
(Initial value)
(Initial value)
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