HD6417615AF60 HITACHI [Hitachi Semiconductor], HD6417615AF60 Datasheet - Page 381

• Manufacturer Part Number: HD6417615AF60
• Description: CMOS single-chip microcontroller
• Manufacturer: HITACHI [Hitachi Semiconductor]

16 bytes are purged in each write, so a purge of 256 bytes of consecutive areas can be
accomplished in 16 writes. Access sizes when associative purges are performed should be
longword. A purge of 1 line requires 2 cycles.
Also note that write-back (flushing) to the main memory is not performed if there is a dirty line in
the cache.
8.4.8
When the CPU rewrites the contents of a specific shared address in the cache by write-back in a
multiprocessor configuration or a configuration in which the chip's internal E-DMAC (or DMAC)
and CPU share memory, the rewritten data must be written back to the main memory, and the
cache contents invalidated, before the bus is granted by the CPU in the chip to another master
(external master, E-DMAC, or DMAC). The chip does not support an instruction or procedure for
flushing the contents of specific addresses, so in order to execute a cache flush it is necessary to
perform reads in a 4-kbyte space (cache area) other than the address space to be flushed from
cache, and intentionally create cache misses. For this purpose, cache accesses should be performed
every 16 bytes. By this means, write-backs are generated and the contents written to the cache by
the CPU in the chip are written back to the main memory, enabling flushing to be executed.
However, this method incurs an overhead consisting of the cache fill time due to read misses and
the time for rereading data to be left in the cache. Therefore, if the overhead due to use of the
write-back method is of concern when constructing a system in which a number of masters share
memory, the shared area should be made a cache-through area in order to maintain coherency.
8.4.9
The cache data array can be read or written directly via the data array read/write area. Byte, word,
or longword access can be used on the data array. Data array accesses are completed in 1 cycle for
a read and 2 cycles for a write. Since only the cache bus is used, the operation can proceed in
parallel even when another master, such as the DMAC, is using the bus. The data array of way 0 is
mapped on H'C0000000 to H'C00003FF, way 1 on H'C0000400 to H'C00007FF, way 2 on
H'C0000800 to H'C0000BFF and way 3 on H'C0000C00 to H'C0000FFF. When the two-way
mode is being used, the area H'C0000000 to H'C00007FF is accessed as 2 kbytes of on-chip
RAM. When the cache is disabled, the area H'C0000000 to H'C0000FFF can be used as 4 kbytes
of on-chip RAM.
Associative purge:
Number of bits
Bit
Address
Cache Flushing
Data Array Access
31
3
010
28
Figure 8.11 Associative Purge Access
Tag address
19
9
address
Entry
6
3
—
4
0
365