HD6417615AF60 HITACHI [Hitachi Semiconductor], HD6417615AF60 Datasheet - Page 305

• Manufacturer Part Number: HD6417615AF60
• Description: CMOS single-chip microcontroller
• Manufacturer: HITACHI [Hitachi Semiconductor]

For the CS0–CS4 spaces, For spaces CS0—CS4, Th and Tf can be set as follows.
CS0—3
CS4
7.5
7.5.1
Seven kinds of synchronous DRAM can be connected: 2-Mbit (128k
16-Mbit (1M 16, 2M 8, and 4M 4), and 64-Mbit (4M 16 and 8M 8). This chip supports
64-Mbit synchronous DRAMs internally divided into two or four banks, and other synchronous
DRAMs internally divided into two banks. Since synchronous DRAM can be selected by the CS
signal, CS2 and CS3 spaces can be connected using a common RAS or other control signal. When
the memory enable bits for DRAM and other memory (DRAM2–DRAM0) in BCR1 are set to
001, CS2 is ordinary space and CS3 is synchronous DRAM space. When the DRAM2–0 bits are
set to 100, CS2 is synchronous DRAM space and CS3 is ordinary space. When the bits are set to
101, both CS2 and CS3 are synchronous DRAM spaces.
Supported synchronous DRAM operating modes are burst read/single write mode (initial setting)
and burst read/burst write mode. The burst length depends on the data bus width, comprising 8
bursts for a 16-bit width, and 4 bursts for a 32-bit width. The data bus width is specified by the SZ
bit in MCR. Burst operation is always performed, so the burst enable (BE) bit in MCR is ignored.
Switching to burst write mode is performed by means of the BWE bit in BCR3.
Control signals for directly connecting synchronous DRAM are the RAS, CAS/OE, RD/WR, CS2
or CS3, DQMUU, DQMUL, DQMLU, DQMLL, and CKE signals Signals other than CS2 and
CS3 are common to every area, and signals other than CKE are valid and fetched only when CS2
or CS3 is true Therefore, synchronous DRAM can be connected in parallel in multiple areas.
CKE is negated (to the low level) only when a self-refresh is performed; otherwise it is always
asserted (to the high level).
Commands can be specified for synchronous DRAM using the RAS, CAS/OE, RD/WR, and
certain address signals. These commands are NOP, auto-refresh (REF), self-refresh (SELF), all-
bank precharge (PALL), specific bank precharge (PRE), row address strobe/bank active (ACTV),
read (READ), read with precharge (READA), write (WRIT), write with precharge (WRITA), and
mode register write (MRS).
Bytes are specified using DQMUU, DQMUL, DQMLU, and DQMLL. The read/write is
performed on the byte whose DQM is low. For 32-bit data, DQMUU specifies 4n address access
and DQMLL specifies 4n + 3 address access. For 16-bit data, only DQMLU and DQMLL are
288
Synchronous DRAM Interface
Synchronous DRAM Direct Connection
Th
0—2
0—7
Tf
0—2
0—5
WCR3
AnSW1, AnSW0 (Th = Tf) n =0—3
Th: A4SW2—0
Tf: A4HW1—0
16), 4-Mbit (256k 16),