HD6417615AF60 HITACHI [Hitachi Semiconductor], HD6417615AF60 Datasheet - Page 318

Manufacturer Part Number

HD6417615AF60

CMOS single-chip microcontroller

Manufacturer

HITACHI [Hitachi Semiconductor]

When a single write is performed in burst write mode, the synchronous DRAM setting is for a

burst length of 4. After data is written in Tc1, empty writes are performed in Tc2, Tc3, and Tc4 by

driving the DQMxx signal high.

These empty cycles increase the memory access time and tend to reduce program execution speed

and DMA transfer speed. Therefore, unnecessary cache-through area accesses should be avoided,

and copy-back should be selected for the cache setting. Also, in DMA transfer, it is important to

use a data structure that allows transfer in 16-bit units.

Note: * DACKn waveform when active-low is specified.

Figure 7.23 (a) Basic Burst Write Timing (Auto-Precharge) I : E other than 1 : 1