MC9S08DZ16 FREESCALE [Freescale Semiconductor, Inc], MC9S08DZ16 Datasheet - Page 233

• Manufacturer Part Number: MC9S08DZ16
• Description: 8-Bit HCS08 Central Processor Unit (CPU)
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Read: Anytime
Write: Anytime for TXEx flags when not in initialization mode; write of 1 clears flag, write of 0 is ignored
12.3.7
This register contains the interrupt enable bits for the transmit buffer empty interrupt flags.
Freescale Semiconductor
TXE[2:0]
Field
2:0
Reset:
Reset:
W
W
R
R
MSCAN Transmitter Interrupt Enable Register (CANTIER)
Transmitter Buffer Empty — This flag indicates that the associated transmit message buffer is empty, and thus
not scheduled for transmission. The CPU must clear the flag after a message is set up in the transmit buffer and
is due for transmission. The MSCAN sets the flag after the message is sent successfully. The flag is also set by
the MSCAN when the transmission request is successfully aborted due to a pending abort request (see
Section 12.3.8, “MSCAN Transmitter Message Abort Request Register
interrupt is pending while this flag is set.
Clearing a TXEx flag also clears the corresponding ABTAKx (see
Abort Acknowledge Register
(see
When listen-mode is active (see
be cleared and no transmission is started.
Read and write accesses to the transmit buffer are blocked, if the corresponding TXEx bit is cleared (TXEx = 0)
and the buffer is scheduled for transmission.
0 The associated message buffer is full (loaded with a message due for transmission)
1 The associated message buffer is empty (not scheduled)
The CANTFLG register is held in the reset state when the initialization
mode is active (INITRQ = 1 and INITAK = 1). This register is writable when
not in initialization mode (INITRQ = 0 and INITAK = 0).
Section 12.3.8, “MSCAN Transmitter Message Abort Request Register
0
0
0
0
7
7
Figure 12-11. MSCAN Transmitter Interrupt Enable Register (CANTIER)
Figure 12-10. MSCAN Transmitter Flag Register (CANTFLG)
= Unimplemented
= Unimplemented
Table 12-11. CANTFLG Register Field Descriptions
6
0
0
6
0
0
MC9S08DZ60 Series Data Sheet, Rev. 4
(CANTAAK)”). When a TXEx flag is set, the corresponding ABTRQx bit is cleared
Section 12.3.2, “MSCAN Control Register 1
0
0
0
0
5
5
NOTE
4
0
0
4
0
0
Description
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
0
0
0
0
3
3
Section 12.3.9, “MSCAN Transmitter Message
(CANTARQ)”). If not masked, a transmit
TXEIE2
TXE2
(CANCTL1)”) the TXEx flags cannot
2
1
2
0
(CANTARQ)”).
TXEIE1
TXE1
1
0
1
1
TXEIE0
TXE0
0
1
0
0
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