MC9S08DZ16 FREESCALE [Freescale Semiconductor, Inc], MC9S08DZ16 Datasheet - Page 382

• Manufacturer Part Number: MC9S08DZ16
• Description: 8-Bit HCS08 Central Processor Unit (CPU)
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Appendix A Electrical Characteristics
382
1
2
3
4
5
6
7
8
Num C
18
19
20
21
22
23
24
25
TRIM register at default value (0x80) and FTRIM control bit at default value (0x0).
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or
changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the
reference, this specification assumes it is already running.
This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it
is already running.
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via V
a given interval. Jitter measurements are based upon a 40MHz MCGOUT clock frequency.
In some specifications, this value is described as “long term accuracy of PLL output clock (averaged over 2 ms)” with symbol
“f
In some specifications, this value is described as “Jitter of PLL output clock measured over 625 ns” with symbol
“f
Below D
MCG is already in lock, then the MCG may stay in lock.
Below D
Table A-12. MCG Frequency Specifications (Temperature Range = –40 to 125°C Ambient) (continued)
pll_jitter_2ms
pll_jitter_625ns
D Lock entry frequency tolerance
D Lock exit frequency tolerance
D Lock time - FLL
D Lock time - PLL
D
D
T
T
lock
unl
RMS frequency variation of a single clock cycle
measured 625 ns after reference edge.
Maximum frequency variation averaged over
625 ns window.
Loss of external clock minimum frequency -
RANGE = 0
Loss of external clock minimum frequency -
RANGE = 1
minimum, the MCG will not exit lock if already in lock. Above D
.” The parameter is unchanged, but the description has been changed for clarification purposes.
minimum, the MCG is guaranteed to enter lock. Above D
.” The parameter is unchanged, but the description has been changed for clarification purposes.
Rating
DD
and V
8
MC9S08DZ60 Series Data Sheet, Rev. 4
7
SS
and variation in crystal oscillator frequency increase the C
6
f
f
pll_maxjit_625ns
pll_cycjit_625ns
Symbol
f
t
f
t
loc_high
pll_lock
loc_low
D
fll_lock
D
lock
unl
lock
maximum, the MCG will not enter lock. But if the
unl
(16/5) x f
maximum, the MCG is guaranteed to exit lock.
(3/5) x f
± 1.49
± 4.47
Min
—
—
—
—
int
int
Typical
0.566
0.113
—
—
—
—
—
—
4
Freescale Semiconductor
1075(1/
1075(1/
t
t
pll_acquire+
fll_acquire+
Jitter
± 2.98
± 5.97
Max
—
—
—
—
f
pll_ref)
f
percentage for
int_t)
BUS
%f
%f
kHz
kHz
.
Unit
%
%
s
s
pll
pll