MC9S08DZ16 FREESCALE [Freescale Semiconductor, Inc], MC9S08DZ16 Datasheet - Page 236

• Manufacturer Part Number: MC9S08DZ16
• Description: 8-Bit HCS08 Central Processor Unit (CPU)
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
Read: Find the lowest ordered bit set to 1, all other bits will be read as 0
Write: Anytime when not in initialization mode
The following gives a short programming example of the usage of the CANTBSEL register:
To get the next available transmit buffer, application software must read the CANTFLG register and write
this value back into the CANTBSEL register. In this example Tx buffers TX1 and TX2 are available. The
value read from CANTFLG is therefore 0b0000_0110. When writing this value back to CANTBSEL, the
Tx buffer TX1 is selected in the CANTXFG because the lowest numbered bit set to 1 is at bit position 1.
Reading back this value out of CANTBSEL results in 0b0000_0010, because only the lowest numbered
bit position set to 1 is presented. This mechanism eases the application software the selection of the next
available Tx buffer.
If all transmit message buffers are deselected, no accesses are allowed to the CANTXFG buffer register.
12.3.11 MSCAN Identifier Acceptance Control Register (CANIDAC)
The CANIDAC register is used for identifier filter acceptance control as described below.
236
TX[2:0]
Field
•
•
•
2:0
Reset:
LDD CANTFLG; value read is 0b0000_0110
STD CANTBSEL; value written is 0b0000_0110
LDD CANTBSEL; value read is 0b0000_0010
W
R
Transmit Buffer Select — The lowest numbered bit places the respective transmit buffer in the CANTXFG
register space (e.g., TX1 = 1 and TX0 = 1 selects transmit buffer TX0; TX1 = 1 and TX0 = 0 selects transmit
buffer TX1). Read and write accesses to the selected transmit buffer will be blocked, if the corresponding TXEx
bit is cleared and the buffer is scheduled for transmission (see
(CANTFLG)”).
0 The associated message buffer is deselected
1 The associated message buffer is selected, if lowest numbered bit
The CANTBSEL register is held in the reset state when the initialization
mode is active (INITRQ = 1 and INITAK=1). This register is writable when
not in initialization mode (INITRQ = 0 and INITAK = 0).
0
0
Figure 12-15. MSCAN Identifier Acceptance Control Register (CANIDAC)
7
= Unimplemented
Table 12-15. CANTBSEL Register Field Descriptions
6
0
0
MC9S08DZ60 Series Data Sheet, Rev. 4
IDAM1
0
5
NOTE
IDAM0
4
0
Description
Section 12.3.6, “MSCAN Transmitter Flag Register
0
0
3
IDHIT2
2
0
Freescale Semiconductor
IDHIT1
0
1
IDHIT0
0
0