MC9S08DZ16 FREESCALE [Freescale Semiconductor, Inc], MC9S08DZ16 Datasheet - Page 57

• Manufacturer Part Number: MC9S08DZ16
• Description: 8-Bit HCS08 Central Processor Unit (CPU)
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

4.5.5
The sector erase abort operation will terminate the active sector erase operation so that other sectors are
available for read and program operations without waiting for the sector erase operation to complete.
The sector erase abort command write sequence is as follows:
If the sector erase abort command is launched resulting in the early termination of an active sector erase
operation, the FACCERR flag will set once the operation completes as indicated by the FCCF flag being
set. The FACCERR flag sets to inform the user that the Flash sector may not be fully erased and a new
sector erase command must be launched before programming any location in that specific sector.
If the sector erase abort command is launched but the active sector erase operation completes normally,
the FACCERR flag will not set upon completion of the operation as indicated by the FCCF flag being set.
Therefore, if the FACCERR flag is not set after the sector erase abort command has completed, a sector
being erased when the abort command was launched will be fully erased.
A flowchart to execute the sector erase abort operation is shown in
Freescale Semiconductor
1. Write to any Flash or EEPROM address to start the command write sequence for the sector erase
2. Write the sector erase abort command, 0x47, to the FCMD register.
3. Clear the FCBEF flag in the FSTAT register by writing a 1 to FCBEF to launch the sector erase
abort command. The address and data written are ignored.
abort command.
Sector Erase Abort
SECTOR ERASE
ABORT FLOW
SECTOR ERASE COMPLETED
Figure 4-4. Sector Erase Abort Flowchart
MC9S08DZ60 Series Data Sheet, Rev. 4
0
1
0
WRITE 0x47 TO FCMD
TO LAUNCH COMMAND
TO BUFFER ADDRESS AND DATA
AND CLEAR FCBEF
WRITE 1 TO FCBEF
SECTOR ERASE ABORTED
WRITE TO Flash
FACCERR?
FCCF?
START
FCCF?
1
1
0
(2)
Figure
(2)
before checking FCBEF or FCCF.
Wait at least four bus cycles
4-4.
Chapter 4 Memory
57