MC9S08DZ16 FREESCALE [Freescale Semiconductor, Inc], MC9S08DZ16 Datasheet - Page 83

• Manufacturer Part Number: MC9S08DZ16
• Description: 8-Bit HCS08 Central Processor Unit (CPU)
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

1
2
5.8.7
This high page register contains status and control bits to support the low-voltage detect function, and to
enable the bandgap voltage reference for use by the ADC and ACMP modules. This register should be
written during the user’s reset initialization program to set the desired controls even if the desired settings
are the same as the reset settings.
Freescale Semiconductor
LVWF will be set in the case when V
This bit can be written only one time after reset. Additional writes are ignored.
Reset:
LVWACK
LVDRE
LVDSE
LVWIE
BGBE
LVWF
LVDE
Field
7
6
5
4
3
2
0
W
R
LVWF
System Power Management Status and Control 1 Register
(SPMSC1)
Low-Voltage Warning Flag — The LVWF bit indicates the low-voltage warning status.
0 low-voltage warning is not present.
1 low-voltage warning is present or was present.
Low-Voltage Warning Acknowledge — If LVWF = 1, a low-voltage condition has occurred. To acknowledge this
low-voltage warning, write 1 to LVWACK, which will automatically clear LVWF to 0 if the low-voltage warning is
no longer present.
Low-Voltage Warning Interrupt Enable — This bit enables hardware interrupt requests for LVWF.
0 Hardware interrupt disabled (use polling).
1 Request a hardware interrupt when LVWF = 1.
Low-Voltage Detect Reset Enable — This write-once bit enables LVD events to generate a hardware reset
(provided LVDE = 1).
0 LVD events do not generate hardware resets.
1 Force an MCU reset when an enabled low-voltage detect event occurs.
Low-Voltage Detect Stop Enable — Provided LVDE = 1, this read/write bit determines whether the low-voltage
detect function operates when the MCU is in stop mode.
0 Low-voltage detect disabled during stop mode.
1 Low-voltage detect enabled during stop mode.
Low-Voltage Detect Enable — This write-once bit enables low-voltage detect logic and qualifies the operation
of other bits in this register.
0 LVD logic disabled.
1 LVD logic enabled.
Bandgap Buffer Enable — This bit enables an internal buffer for the bandgap voltage reference for use by the
ADC and ACMP modules on one of its internal channels.
0 Bandgap buffer disabled.
1 Bandgap buffer enabled.
Figure 5-9. System Power Management Status and Control 1 Register (SPMSC1)
0
7
1
= Unimplemented or Reserved
LVWACK
0
0
6
Table 5-10. SPMSC1 Register Field Descriptions
Supply
MC9S08DZ60 Series Data Sheet, Rev. 4
LVWIE
transitions below the trip point or after reset and V
0
5
LVDRE
1
4
2
Description
Chapter 5 Resets, Interrupts, and General System Control
LVDSE
3
1
LVDE
1
2
2
Supply
is already below V
0
0
1
BGBE
LVW
0
0
.
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