MC9S08DZ16 FREESCALE [Freescale Semiconductor, Inc], MC9S08DZ16 Datasheet - Page 266

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MC9S08DZ16

Manufacturer Part Number
MC9S08DZ16
Description
8-Bit HCS08 Central Processor Unit (CPU)
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
The MSCAN is able to leave sleep mode (wake up) only when:
After wake-up, the MSCAN waits for 11 consecutive recessive bits to synchronize to the CAN bus. As a
consequence, if the MSCAN is woken-up by a CAN frame, this frame is not received.
The receive message buffers (RxFG and RxBG) contain messages if they were received before sleep mode
was entered. All pending actions will be executed upon wake-up; copying of RxBG into RxFG, message
aborts and message transmissions. If the MSCAN remains in bus-off state after sleep mode was exited, it
continues counting the 128 occurrences of 11 consecutive recessive bits.
266
CAN bus activity occurs and WUPE = 1
or
the CPU clears the SLPRQ bit
The CPU cannot clear the SLPRQ bit before sleep mode (SLPRQ = 1 and
SLPAK = 1) is active.
Figure 12-45. Simplified State Transitions for Entering/Leaving Sleep Mode
StartUp
CAN Activity &
SLPRQ
CAN Activity &
SLPRQ
CAN Activity
MC9S08DZ60 Series Data Sheet, Rev. 4
CAN Activity
CAN Activity
Message
Active
for Idle
Tx/Rx
Wait
Idle
NOTE
SLPRQ
CAN Activity
(CAN Activity & WUPE) | SLPRQ
Sleep
(CAN Activity & WUPE) |
CAN Activity
Freescale Semiconductor

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