MC9S08DZ16 FREESCALE [Freescale Semiconductor, Inc], MC9S08DZ16 Datasheet - Page 91

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MC9S08DZ16

Manufacturer Part Number
MC9S08DZ16
Description
8-Bit HCS08 Central Processor Unit (CPU)
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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6.5.1.3
6.5.1.4
Note: Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew
Freescale Semiconductor
PTAPE[7:0]
PTASE[7:0]
Reset:
Reset:
Field
Field
7:0
7:0
rate control to the desired value to ensure correct operation.
W
W
R
R
PTAPE7
PTASE7
Internal Pull Enable for Port A Bits — Each of these control bits determines if the internal pull-up or pull-down
device is enabled for the associated PTA pin. For port A pins that are configured as outputs, these bits have no
effect and the internal pull devices are disabled.
0 Internal pull-up/pull-down device disabled for port A bit n.
1 Internal pull-up/pull-down device enabled for port A bit n.
Output Slew Rate Enable for Port A Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.
Port A Pull Enable Register (PTAPE)
0
Port A Slew Rate Enable Register (PTASE)
0
7
7
Pull-down devices only apply when using pin interrupt functions, when
corresponding edge select and pin select functions are configured.
PTAPE6
PTASE6
Figure 6-5. Internal Pull Enable for Port A Register (PTAPE)
Figure 6-6. Slew Rate Enable for Port A Register (PTASE)
0
0
6
6
Table 6-3. PTAPE Register Field Descriptions
Table 6-4. PTASE Register Field Descriptions
PTAPE5
PTASE5
MC9S08DZ60 Series Data Sheet, Rev. 4
0
0
5
5
PTAPE4
PTASE4
NOTE
0
0
4
4
Description
Description
PTAPE3
PTASE3
3
0
3
0
PTAPE2
PTASE2
Chapter 6 Parallel Input/Output Control
0
0
2
2
PTAPE1
PTASE1
0
0
1
1
PTAPE0
PTASE0
0
0
0
0
91

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