MC9S08DZ16 FREESCALE [Freescale Semiconductor, Inc], MC9S08DZ16 Datasheet - Page 37

• Manufacturer Part Number: MC9S08DZ16
• Description: 8-Bit HCS08 Central Processor Unit (CPU)
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

1
2
3.6
One of two stop modes is entered upon execution of a STOP instruction when the STOPE bit in SOPT1
register is set. In both stop modes, all internal clocks are halted. The MCG module can be configured to
leave the reference clocks running. See
more information.
Table 3-1
conditions. The selected mode is entered following the execution of a STOP instruction.
3.6.1
Stop3 mode is entered by executing a STOP instruction under the conditions as shown in
states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained.
Exit from stop3 is done by asserting RESET or an asynchronous interrupt pin. The asynchronous interrupt
pins are IRQ, PIA0–PIA7, PIB0–PIB7, and PID0–PID7. Exit from stop3 can also be done by the
low-voltage detect (LVD) reset, low-voltage warning (LVW) interrupt, ADC conversion complete
interrupt, real-time clock (RTC) interrupt, MSCAN wake-up interrupt, or SCI receiver interrupt.
If stop3 is exited by means of the RESET pin, the MCU will be reset and operation will resume after
fetching the reset vector. Exit by means of an interrupt will result in the MCU fetching the appropriate
interrupt vector.
3.6.1.1
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below
the LVD voltage. If the LVD is enabled in stop (LVDE and LVDSE bits in SPMSC1 both set) at the time
the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode.
For the ADC to operate the LVD must be left enabled when entering stop3.
Freescale Semiconductor
STOPE
ENBDM is located in the BDCSCR, which is only accessible through BDC commands, see
Control Register
When in Stop3 mode with BDM enabled, The S
0
1
1
1
1
Stop Modes
shows all of the control bits that affect stop mode selection and the mode selected under various
ENBDM
Stop3 Mode
LVD Enabled in Stop3 Mode
1
0
0
0
x
(BDCSCR)”.
1
Both bits must be 1
LVDE
Either bit a 0
Either bit a 0
x
x
LVDSE
MC9S08DZ60 Series Data Sheet, Rev. 4
Table 3-1. Stop Mode Selection
PPDC
Chapter 8, “Multi-Purpose Clock Generator
x
x
x
0
1
IDD
will be near R
Stop modes disabled; illegal opcode reset if STOP instruction executed
Stop3 with BDM enabled
Stop3 with voltage regulator active
Stop3
Stop2
IDD
levels because internal clocks are enabled.
2
Stop Mode
Section 17.4.1.1, “BDC Status and
Chapter 3 Modes of Operation
(S08MCGV1),” for
Table
3-1. The
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