M30622SAFP MITSUBISHI [Mitsubishi Electric Semiconductor], M30622SAFP Datasheet - Page 132

• Manufacturer Part Number: M30622SAFP
• Description: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]

Clock asynchronous serial I/O (UART) mode
132
Figure 1.16.22. Typical transmit/receive timing in UART mode (used for the SIM interface)
Note 1: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.
Note 2: Equal in waveform because TxD2 and RxD2 are connected.
Transfer clock
Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
TxD
RxD
Signal conductor level
(Note 2)
Transmit register
empty flag (TXEPT)
Transmit interrupt
request bit (IR)
Transfer clock
Receive enable
bit (RE)
RxD
TxD
Signal conductor level
(Note)
Receive complete
flag (RI)
Receive interrupt
request bit (IR)
Note: Equal in waveform because TxD
2
2
2
2
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
The above timing applies to the following settings :
Shown in ( ) are bit symbols.
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “0”.
“1”
“0”
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “1”.
ST
ST
Start
Start
ST
ST
bit
bit
D
D
D
D
0
0
0
0
Data is set in UART2 transmit buffer register
D
D
D
D
2
1
1
1
1
Tc
and RxD
Tc
D
D
D
D
2
2
2
2
D
D
D
D
3
3
3
3
D
D
D
D
2
4
4
4
4
are connected.
D
D
D
D
5
5
5
5
D
D
Transferred from UART2 transmit buffer register to UART2 transmit register
D
D
6
6
6
6
D
D
D
D
Parity
Parity
7
7
7
7
bit
bit
Cleared to “0” when interrupt request is accepted, or cleared by software
Tc = 16 (n + 1) / fi
Tc = 16 (n + 1) / fi
P
P
P
P
Cleared to “0” when interrupt request is accepted, or cleared by software
SP
SP
SP
SP
fi : frequency of BRG2 count source (f
n : value set to BRG2
fi : frequency of BRG2 count source (f
n : value set to BRG2
Stop
Stop
bit
bit
Read to receive buffer
ST
ST
ST
Note 1
The level is detected by the
interrupt routine.
ST
A “L” level returns from TxD
the occurrence of a parity error.
A “L” level returns from TxD
the occurrence of a parity error.
D
D
D
D
0
0
0
0
D
D
D
D
1
1
1
1
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D
D
D
D
2
2
2
2
D
D
D
D
3
3
3
3
D
D
D
D
4
4
4
4
D
D
1
D
1
D
5
5
, f
, f
5
2
5
2
8
due to
8
D
D
D
, f
, f
due to
D
6
6
6
6
32
32
D
D
D
)
D
)
7
7
7
7
P
P
P
P
Read to receive buffer
M16C / 62A Group
SP
Mitsubishi microcomputers
SP
SP
SP
The level is
detected by the
interrupt routine.