M30622SAFP MITSUBISHI [Mitsubishi Electric Semiconductor], M30622SAFP Datasheet - Page 141

• Manufacturer Part Number: M30622SAFP
• Description: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]

UART2 Special Mode Register 2
Figure 1.16.30. Functional block diagram for I
P7
P7
P7
Functions available in I
Bit 3 of the UART2 special mode register 2 (address 0376
this bit to “1” causes an arbitration loss to occur, and the SDA pin turns to high-impedance state the
instant when the arbitration loss detection flag is set to “1”.
Bit 1 of the UART2 special mode register 2 (address 0376
With this bit set to “1” at the time when the internal SCL is set to “H”, the internal SCL turns to “L” if the
falling edge is found in the SCL pin; and the baud rate generator reloads the set value, and start counting
within the “L” interval. When the internal SCL changes from “L” to “H” with the SCL pin set to “L”, stops
counting the baud rate generator, and starts counting it again when the SCL pin turns to “H”. Due to this
function, the UART2 transmission-reception clock becomes the logical product of the signal flowing
through the internal SCL and that flowing through the SCL pin. This function operates over the period
from the moment earlier by a half cycle than falling edge of the UART2 first clock to the rising edge of the
ninth bit. To use this function, choose the internal clock for the transfer clock.
Bit 2 of the UART2 special mode register 2 (0376
“1” causes the SCL pin to be fixed to “L” at the falling edge of the ninth bit of the clock. Setting this bit to
“0” frees the output fixed to “L”.
P7
0
2
1
/TxD
/CLK
/RxD
0
2
2
through P7
2
/SDA
/SCL
Filter
Filter
Noize
Noize
2
Noize
Filter
Selector
conforming to the simplified I C bus
Digital delay
(Divider)
Timer
Selector
Selector
UART2
Falling edge
detection
2
Timer
I/O
IICM=1
IICM=0
C mode are shown in Figure 1.16.30 — a functional block diagram.
SDDS=1 and
DL 000
SDDS=0
or DL=000
IICM=1
UART2
IICM=0
UART2
D
(Port P7
T
I/O
Q
Start condition
detection
Stop condition
detection
Timer
I/O
Q
IICM=1
IICM=0
1
R
output data latch)
L-synchronous
output enabling
bit
External clock
Internal clock
Data bus
Port reading
*
With IICM set to 1, the port terminal is to be readable
even if 1 is assigned to P7
SDHI
SWC2
IICM=1 (SDDS=0) or
DL=000 (SDDS=1)
IICM=0 or
DL 000 (SDDS=1)
2
S
R
Analog
Q
delay
Arbitration
CLK
control
Reception register
ALS
Bus busy
UART2
Falling edge of 9 bit
2
UART2
C mode
Bus collision
detection
9th pulse
16
Transmission
register
SWC
D
D
UART2
T
T
) is used as the SCL wait output bit. Setting this bit to
Q
Q
1
of the direction register.
ACK
IICM=1
IICM=0
NACK
16
IICM=1
and IICM2=0
16
IICM=0
or IICM2=1
) is used as the SDA output stop bit. Setting
IICM=1
and IICM2=0
IICM=0
or IICM2=1
) is used as the clock synchronization bit.
Bus collision/start, stop condition
detection interrupt request
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 reception/ACK interrupt
request, DMA1 request
UART2 transmission/
NACK interrupt request
M16C / 62A Group
Mitsubishi microcomputers
To DMA0
To DMA0, DMA1
141