M30622SAFP MITSUBISHI [Mitsubishi Electric Semiconductor], M30622SAFP Datasheet - Page 241
M30622SAFP
Manufacturer Part Number
M30622SAFP
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Manufacturer
MITSUBISHI [Mitsubishi Electric Semiconductor]
Datasheet
1.M30622SAFP.pdf
(274 pages)
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Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
Overview of standard serial I/O mode 1 (clock synchronized)
In standard serial I/O mode 1, software commands, addresses and data are input and output between the
MCU and peripheral units (serial programer, etc.) using 4-wire clock-synchronized serial I/O (UART1).
Standard serial I/O mode 1 is engaged by releasing the reset with the P5
(CLK
) pin "H" level.
6
1
In reception, software commands, addresses and program data are synchronized with the rise of the
transfer clock that is input to the CLK
pin, and are then input to the MCU via the RxD
pin. In transmis-
1
1
sion, the read data and status are synchronized with the fall of the transfer clock, and output from the
TxD
pin.
1
The TxD
pin is for CMOS output. Transfer is in 8-bit units with LSB first.
1
When busy, such as during transmission, reception, erasing or program execution, the RTS
(BUSY) pin
1
is "H" level. Accordingly, always start the next transfer after the RST
(BUSY) pin is "L" level.
1
Also, data and status registers in memory can be read after inputting software commands. Status, such
as the operating state of the flash memory or whether a program or erase operation ended successfully or
not, can be checked by reading the status register. Here following are explained software commands,
status registers, etc.
241
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