M30622SAFP MITSUBISHI [Mitsubishi Electric Semiconductor], M30622SAFP Datasheet - Page 133
M30622SAFP
Manufacturer Part Number
M30622SAFP
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Manufacturer
MITSUBISHI [Mitsubishi Electric Semiconductor]
Datasheet
1.M30622SAFP.pdf
(274 pages)
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Clock asynchronous serial I/O (UART) mode
Figure 1.16.23. Output timing of the parity error signal
Figure 1.16.24. SIM interface format
(a) Function for outputting a parity error signal
(b) Direct format/inverse format
With the error signal output enable bit (bit 7 of address 037D
level from the TxD
of a transmission completion interrupt changes to the detection timing of a parity error signal. Figure
1.16.23 shows the output timing of the parity error signal.
Connecting the SIM card allows you to switch between direct format and inverse format. If you choose
the direct format, D
and output from TxD
Figure 1.16.24 shows the SIM interface format.
complete flag
• LSB first
Transfer
Receive
(inverse)
Transfer
(direct)
RxD
TxD
clock
TxD
TxD
clcck
2
2
2
2
2
“H”
“H”
“H”
“L”
“L”
“L”
“1”
“0”
0
pin when a parity error is detected. In step with this function, the generation timing
2
data is output from TxD
.
ST
D0
D0
D7
D1
D1
D6
D2
D2
D5
2
. If you choose the inverse format, D
D3
D3
D4
Hi-Z
D4
D4
D3
D5
D5
D2
16
) assigned “1”, you can output an “L”
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D6
D6
D1
ST : Start bit
P : Even Parity
SP : Stop bit
D7
D7
D0
P
P
P
P : Even parity
SP
M16C / 62A Group
Mitsubishi microcomputers
7
data is inverted
133
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