HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 175

• Manufacturer Part Number: HD6433044
• Description: (HD64 Series) Hitachi Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

Refresh Cycle Priority Order: When there are simultaneous bus requests, the priority order is:
For details see section 6.3.7, Bus Arbiter Operation.
Wait State Insertion: When bit AST3 is set to 1 in ASTCR, bus controller settings can cause wait
states to be inserted into bus cycles and refresh cycles. For details see section 6.3.5, Wait Modes.
ø
Address
bus
(
(
(
(
Note:
CS
RAS
HWR
UCAS
LWR
LCAS
RD
WE
RFSH
AS
(High)
3
)
)
*
)
)
16-bit access
Figure 7-5 DRAM Control Signal Output Timing (2) (2CAS Mode)
External bus master > refresh controller > DMA controller > CPU
Row
Read cycle
Column
Row
Write cycle
161
Column
*
Area 3 top address
Refresh cycle
(Low)