HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 654

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HD6433044

Manufacturer Part Number
HD6433044
Description
(HD64 Series) Hitachi Single-Chip Microcomputer
Manufacturer
Hitachi Semiconductor
Datasheet

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20.2.2 Module Standby Control Register (MSTCR)
MSTCR is an 8-bit readable/writable register that controls output of the system clock (ø). It also
controls the module standby function, which places individual on-chip supporting modules in the
standby state. Module standby can be designated for the ITU, SCI0, SCI1, DMAC, refresh
controller, and A/D converter modules.
MSTCR is initialized to H'40 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—ø Clock Stop (PSTOP): Enables or disables output of the system clock (ø).
Bit 1
PSTOP
0
1
Bit 6—Reserved: Read-only bit, always read as 1.
Bit 5—Module Standby 5 (MSTOP5): Selects whether to place the ITU in standby.
Bit 5
MSTOP5 Description
0
1
Bit
Initial value
Read/Write
Description
System clock output is enabled
System clock output is disabled
ITU operates normally
ITU is in standby state
PSTOP
ø clock stop
Enables or disables
output of the system clock
R/W
7
0
Reserved bit
6
1
MSTOP5
R/W
5
0
645
MSTOP4
R/W
4
0
Module standby 5 to 0
These bits select modules
to be placed in standby
MSTOP3
R/W
3
0
MSTOP2
R/W
2
0
MSTOP1
R/W
1
0
(Initial value)
(Initial value)
MSTOP0
R/W
0
0

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