HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 505

• Manufacturer Part Number: HD6433044
• Description: (HD64 Series) Hitachi Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

The receive margin in asynchronous mode can therefore be expressed as in equation (1).
M = | (0.5 –
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
From equation (1), if F = 0 and D = 0.5 the receive margin is 46.875%, as given by equation (2).
D = 0.5, F = 0
M = {0.5 – 1/(2 16)} 100%
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
= 46.875%.................................................................................................(2)
Internal
base clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
Figure 13-21 Receive Data Sampling Timing in Asynchronous Mode
2N
1
) – (L – 0.5) F –
0
8 clocks
Start bit
16 clocks
| D – 0.5 |
7
N
(1 + F) |
494
15 0
100%
...................(1)
D
0
7
15 0
D
1