HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 661

• Manufacturer Part Number: HD6433044
• Description: (HD64 Series) Hitachi Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

20.6 Module Standby Function
20.6.1 Module Standby Timing
The module standby function can halt several of the on-chip supporting modules (the ITU, SCI0,
SCI1, DMAC, refresh controller, and A/D converter) independently of the power-down state. This
standby function is controlled by bits MSTOP5 to MSTOP0 in MSTCR. When one of these bits is
set to 1, the corresponding on-chip supporting module is placed in standby and halts at the
beginning of the next bus cycle after the MSTCR write cycle.
20.6.2 Read/Write in Module Standby
When an on-chip supporting module is in module standby, read/write access to its registers is
disabled. Read access always results in H'FF data. Write access is ignored.
20.6.3 Usage Notes
When using the module standby function, note the following points.
DMAC and Refresh Controller: When setting bit MSTOP2 or MSTOP1 to 1 to place the DMAC
or refresh controller in module standby, make sure that the DMAC or refresh controller is not
currently requesting the bus right. If bit MSTOP2 or MSTOP1 is set to 1 when a bus request is
present, operation of the bus arbiter becomes ambiguous and a malfunction may occur.
Internal Peripheral Module Interrupt: When MSTCR is set to “1”, prevent module interrupt in
advance. When an on-chip supporting module is placed in standby by the module standby
function, its registers are initialized.
Pin States: Pins used by an on-chip supporting module lose their module functions when the
module is placed in module standby. What happens after that depends on the particular pin. For
details, see section 9, I/O Ports. Pins that change from the input to the output state require special
care. For example, if SCI1 is placed in module standby, the receive data pin loses its receive data
function and becomes a generic I/O pin. If its data direction bit is set to 1, the pin becomes a data
output pin, and its output may collide with external serial data. Data collisions should be
prevented by clearing the data direction bit to 0 or taking other appropriate action.
Register Resetting: When an on-chip supporting module is halted by the module standby
function, all its registers are initialized. To restart the module, after its MSTOP bit is cleared to 0,
its registers must be set up again. It is not possible to write to the registers while the MSTOP bit is
set to 1.
MSTCR Access from DMAC Disabled: To prevent malfunctions, MSTCR can only be accessed
from the CPU. It can be read by the DMAC, but it cannot be written by the DMAC.
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