HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 62

• Manufacturer Part Number: HD6433044
• Description: (HD64 Series) Hitachi Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

2.8.2 Program Execution State
In this state the CPU executes program instructions in normal sequence.
2.8.3 Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal
program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from
the exception vector table and branches to that address. In interrupt and trap exception handling
the CPU references the stack pointer (ER7) and saves the program counter and condition code
register.
Types of Exception Handling and Their Priority: Exception handling is performed for resets,
interrupts, and trap instructions. Table 2-14 indicates the types of exception handling and their
priority. Trap instruction exceptions are accepted at all times in the program execution state.
Table 2-14 Exception Handling Types and Priority
Priority Type of Exception Detection Timing
High
Low
Note: * Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or
Figure 2-12 classifies the exception sources. For further details about exception sources, vector
numbers, and vector addresses, see section 4, Exception Handling, and section 5, Interrupt
Controller.
immediately after reset exception handling.
Reset
Interrupt
Trap instruction
Synchronized with clock
End of instruction
execution or end of
exception handling*
When TRAPA instruction
is executed
47
Start of Exception Handling
Exception handling starts immediately
when
When an interrupt is requested,
exception handling starts at the end of
the current instruction or current
exception-handling sequence
Exception handling starts when a trap
(TRAPA) instruction is executed
RES changes from low to high