K9F5608D0D SAMSUNG [Samsung semiconductor], K9F5608D0D Datasheet - Page 9

• Manufacturer Part Number: K9F5608D0D
• Description: 32M x 8 Bit NAND Flash Memory
• Manufacturer: SAMSUNG [Samsung semiconductor]

PRODUCT INTRODUCTION
The K9F5608X0D is a 264Mbit(276,824,064 bit) memory organized as 65,536 rows(pages) by 528 columns. Spare eight columns are
located from column address of 512~527. A 528-byte data register is connected to memory cell arrays accommodating data transfer
between the I/O buffers and memory during page read and page program operations.The memory array is made up of 16 cells that
are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of two NAND struc-
tured strings. A NAND structure consists of 16 cells. Total 135168 NAND cells reside in a block. The array organization is shown in
Figure 2-1. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis.
The memory array consists of 2048 separately erasable 16K-Byte blocks. It indicates that the bit by bit erase operation is prohibited
on the K9F5608X0D.
The K9F5608X0D has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts while providing high perfor-
mance and allows systems upgrades to future densities by maintaining consistency in system board design. Command, address and
data are all written through I/O′s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch
Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some com-
mands require one bus cycle. For example, Reset command, Read command, Status Read command, etc require just one cycle bus.
Some other commands like Page Program and Copy-back Program and Block Erase, require two cycles: one cycle for setup and the
other cycle for execution. The 32M-byte physical space requires 24 addresses, thereby requiring three cycles for word-level address-
ing: column address, low row address and high row address, in that order. Page Read and Page Program need the same three
address cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used.
Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of
the K9F5608X0D.
The device includes one block sized OTP(One Time Programmable), which can be used to increase system security or to provide
identification capabilities. Detailed information can be obtained by contact with Samsung.
Table 1. COMMAND SETS
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
K9F5608R0D
K9F5608U0D
Read 1
Read 2
Read ID
Reset
Page Program
Copy-Back Program
Block Erase
Read Status
Function
K9F5608D0D
1st. Cycle
00h/01h
FFh
50h
90h
80h
00h
60h
70h
9
2nd. Cycle
8Ah
D0h
10h
-
-
-
-
-
Acceptable Command during Busy
FLASH MEMORY
O
O