AX88796BLI ASIX [ASIX Electronics Corporation], AX88796BLI Datasheet - Page 50

• Manufacturer Part Number: AX88796BLI
• Description: Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller
• Manufacturer: ASIX [ASIX Electronics Corporation]

5.1.66 Inter-frame gap (IFG)
Offset 16H (Read/Write)
Offset 17H (Write)
5.1.68 Device Status Register (DSR)
Offset 17H (Read)
5.1.69 MAX Frame Size Register (MFSR0)
Offset 18H (Read/Write)
5.1.70 MAX Frame Size Register (MFSR1)
Offset 19H (Read/Write)
Field
7
6:0
5.1.67 Back-pressure Jam Limit Count (BJLC)
Field
7:6
5:0
Field
7
6
5
4
3
2
1
0
Field
7:0
Field
7:3
2:0
-
-
BJLC
B_ENDIAN
RD_RDY
D_RDY
I_SPEED
I_LINK
MFSR0
Name
IFG
Name
Name
RDMA_RDY Remote DMA completed. It is same as ISR bit 6.
-
I_DUPLEX
Name
Name
-
MFSR1
Description (Default = 15h)
Reserved, Always zero.
Inter-frame Gap for Back-To-Back Transmission without collision
Description
Reserved, Always zero.
Back-pressure Jam Limit count, Default value is 19H.
Description (Default = 00h)
MAX Frame size [7:0], default {MFSR1, MFSR0} = 1536 bytes
Description (Default = 06h)
Reserved
MAX Frame size [10:8]
Description
When set indicates big-endian mode. (The Big-endian Register’s value not all zero)
When set, it indicates the remote DMA process was completed.
Read Data Port Ready, When set, indicates data was ready from SRAM to data port for
host reading.
Device Ready. When set, this bit indicates that AX88796B is ready to be accessed. This
register can be read when AX88796B in any power management mode.
When cleared, indicate AX88796B in reset, power saving or load EEPROM state.
Always zero
PHY Link Speed:
0: indicate the link speed is 10Mb/s
1: indicate the link speed is 100Mb/s
PHY Duplex mode:
0: half-duplex
1: full-duplex
Link Status:
0: Link off
1: Link up
15h (default)
15h + n
15h – n
IFG
50
AX88796BLF / AX88796BLI
ASIX ELECTRONICS CORPORATION
Bit-time of Frame gap
96 + (4*n)
96 – (4*n)
96