MT46H16M32LFCX-5:B Micron Technology Inc, MT46H16M32LFCX-5:B Datasheet
MT46H16M32LFCX-5:B
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MT46H16M32LFCX-5:B Summary of contents
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Mobile Low-Power DDR SDRAM MT46H32M16LF – 8 Meg Banks MT46H16M32LF – 4 Meg Banks Features • 1.70–1.95V DD DDQ • 1.2V I/O option V = 1.14–1.30V DDQ • Bidirectional ...
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Table 2: Configuration Addressing 512 Architecture 32 Meg x 16 Configuration 8 Meg banks Refresh count Row addressing A[12:0] Column addressing A[9:0] Figure 1: 512Mb Mobile LPDDR Part Numbering MT Micron Technology Product Family 46 = ...
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Contents General Description ......................................................................................................................................... 8 Functional Block Diagrams ............................................................................................................................... 9 Ball Assignments and Descriptions ................................................................................................................. 11 Package Dimensions ...................................................................................................................................... 15 Electrical Specifications .................................................................................................................................. 18 Electrical Specifications – I Parameters ........................................................................................................ 22 DD Electrical Specifications – AC Operating Conditions ......................................................................................... 26 ...
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Rev. E, Production – 8/08 ............................................................................................................................ 96 Rev. D, Production – 05/08 .......................................................................................................................... 96 Rev. C, Production – 03/08 .......................................................................................................................... 97 Rev. B, Preliminary – 12/07 ......................................................................................................................... 97 Rev. A, Advance – 7/07 ................................................................................................................................ 97 Revision History for Commands, Operations, ...
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List of Tables Table 1: Key Timing Parameters ( .......................................................................................................... 1 Table 2: Configuration Addressing 512 ............................................................................................................. 2 Table 3: VFBGA Ball Descriptions .................................................................................................................. 13 Table 4: Absolute Maximum Ratings .............................................................................................................. 18 Table 5: AC/DC Electrical Characteristics and ...
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List of Figures Figure 1: 512Mb Mobile LPDDR Part Numbering ............................................................................................. 2 Figure 2: Functional Block Diagram (x16) ......................................................................................................... 9 Figure 3: Functional Block Diagram (x32) ....................................................................................................... 10 Figure 4: 60-Ball VFBGA – 8mm x 9mm (Top View) ......................................................................................... 11 ...
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Figure 51: Power-Down Entry (in Active or Precharge Mode) .......................................................................... 92 Figure 52: Power-Down Mode (Active or Precharge) ....................................................................................... 93 Figure 53: Deep Power-Down Mode .............................................................................................................. 94 Figure 54: Clock Stop Mode ........................................................................................................................... 95 PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I ...
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General Description The 512Mb Mobile DDR SDRAM is a high-speed CMOS, dynamic random-access mem- ory containing 536,870,912 bits internally configured as a quad-bank DRAM. Each of the x16’s 134,217,728-bit banks is organized as 8,192 rows by 1,024 columns ...
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... BA0, BA1 register PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM Bank 2 Bank 1 Bank 0 Row- address row- Bank 0 address Mux memory latch array and decoder Sense amplifiers I/O gating 2 DM mask logic Bank control logic 2 Column decoder ...
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... PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM Bank 2 Bank 1 Refresh counter Bank 0 Row- row- address Bank 0 address MUX memory latch array and decoder Sense amplifiers I/O gating 2 DM mask logic Bank control logic 2 Column decoder ...
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Ball Assignments and Descriptions Figure 4: 60-Ball VFBGA – 8mm x 9mm (Top View test pin that must be tied to V Note: PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf ...
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Figure 5: 90-Ball VFBGA – 10mm x 13mm and 9mm x 13mm (Top View test pin that must be tied to ...
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... Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ or WRITE commands, to select one location out of the memory array in the respective bank. During a PRECHARGE command, A10 determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA0, BA1) or all banks (A10 HIGH) ...
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Table 3: VFBGA Ball Descriptions (Continued) Symbol DNU/A13 PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM Type Description V Supply DQ power supply. DDQ V Supply DQ ground. SSQ V Supply Power supply. DD ...
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Package Dimensions Figure 6: 60-Ball VFBGA (8mm x 9mm) Seating plane A 0.1 A 60x Ø0.45 Dimensions apply to solder balls post-reflow. The pre-reflow balls are Ø0.42 on Ø0.4 SMD ball pads. 3.6 7.2 0.8 TYP 0.8 ...
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Figure 7: 90-Ball VFBGA (10mm x 13mm) Seating plane A 0.1 A 90X Ø0.45 Dimensions apply to solder balls post-reflow. The pre-reflow balls are Ø0.42 on Ø0 SMD ball pads. 5.6 11.2 0.8 TYP 3.2 1. All dimensions ...
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Figure 8: 90-Ball VFBGA (9mm x 13mm) Seating plane A 0.12 A 90X Ø0.45 Solder ball material: SAC105. Dimensions apply to solder balls post reflow on Ø0.4 SMD ball pads. 11.2 CTR 0.8 TYP 1. All dimensions ...
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Electrical Specifications Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other condi- tions above those indicated in the operational sections ...
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Table 5: AC/DC Electrical Characteristics and Operating Conditions (Continued) Notes 1–5 apply to all parameters/conditions in this table; V Parameter/Condition Output leakage current (DQ are disabled; 0V ≤ V ≤ V OUT DDQ Operating temperature Commercial Industrial Table 6: 1.2V ...
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Tests for AC timing Outputs measured with equivalent load; transmission line delay is assumed to be very 5. Timing and I 6. Any positive glitch must be less than one-third of the clock cycle and not more ...
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The I/O capacitance per DQS and DQ byte/group will not differ by more than this maxi- PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM mum amount for any given device. 21 Electrical Specifications ...
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Electrical Specifications – I Table 8: I Specifications and Conditions (x16) DD Notes 1–5 apply to all parameters/conditions in this table; V Parameter/Condition Operating 1 bank active precharge current (MIN); CKE is HIGH HIGH between valid ...
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Table 9: I Specifications and Conditions (x32) DD Notes 1–5 apply to all parameters/conditions in this table; V Parameter/Condition Operating 1 bank active precharge current (MIN); CKE is HIGH HIGH between valid commands; Ad- dress inputs ...
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Table 10: I Specifications and Conditions DD6 Notes 1–5, 7, and 12 apply to all parameters/conditions in this table; V Parameter/Condition Self refresh t t CKE = LOW (MIN); Address and control inputs are stable; Data bus ...
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Figure 9: Typical Self Refresh Current vs. Temperature 700 650 600 550 500 450 400 350 300 250 200 150 100 –40 –35 –30 –25 –20 –15 –10 –5 PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 ...
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Electrical Specifications – AC Operating Conditions Table 11: Electrical Characteristics and Recommended AC Operating Conditions Notes 1–9 apply to all parameters in this table; V Parameter Access window from CK/CK# Clock cycle ...
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Table 11: Electrical Characteristics and Recommended AC Operating Conditions (Continued) Notes 1–9 apply to all parameters in this table; V Parameter Half-clock period Data-out High window from CK/CK# Data-out Low-Z window from CK/CK# ...
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Table 11: Electrical Characteristics and Recommended AC Operating Conditions (Continued) Notes 1–9 apply to all parameters in this table; V Parameter DQS read postamble Active bank a to active bank b command Read of SRR to next valid command SRR ...
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CAS latency definition: with the first data element is valid Timing tests may use a V 10. Clock frequency is only permitted to change during clock stop, power-down, or self re- 11. In ...
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Output Drive Characteristics Table 12: Target Output Drive Characteristics (Full Strength) Notes 1–2 apply to all values; characteristics are specified under best and worst process variations/conditions Voltage (V) 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.85 0.90 0.95 ...
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Table 13: Target Output Drive Characteristics (Three-Quarter Strength) Notes 1–3 apply to all values; characteristics are specified under best and worst process variations/conditions Voltage (V) 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.85 0.90 0.95 1.00 1.10 1.20 ...
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Table 14: 1.2V I/O Target Output Drive Characteristics (Three-Quarter Strength) Notes 1–3 apply to all values; characteristics are specified under best and worst process variations/conditions Voltage (V) 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10 1.20 ...
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Table 15: Target Output Drive Characteristics (One-Half Strength) Notes 1–3 apply to all values; characteristics are specified under best and worst process variations/conditions Voltage (V) 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.85 0.90 0.95 1.00 1.10 1.20 ...
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... An auto refresh mode is provided, along with a power-saving power-down mode. Deep power-down mode is offered to achieve maximum power reduction by eliminating the power of the memory array. Data will not be retained after the device enters deep power- down mode. Two self refresh features, temperature-compensated self refresh (TCSR) and partial-ar- ray self refresh (PASR), offer additional power savings ...
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Commands A quick reference for available commands is provided in Table 16 and Table 17 (page 36), followed by a written description of each command. Three additional truth tables (Table 18 (page 42), Table 19 (page 43), and Table 20 ...
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Table 17: DM Operation Truth Table Name (Function) Write enable Write inhibit 1. Used to mask write data; provided coincident with the corresponding data. Notes: 2. All states and sequences not shown are reserved and/or illegal. DESELECT The DESELECT function ...
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Figure 10: ACTIVE Command RAS# CAS# Address BA0, BA1 READ The READ command is used to initiate a burst read access to an active row. The values on the BA0 and BA1 inputs select the bank; the address provided on ...
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... Input data appearing on the DQ is written to the memory array, subject to the DM input logic level appearing coincident with the data given DM signal is registered LOW, the corresponding data will be written to memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location ...
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Figure 12: WRITE Command RAS# CAS# Address BA0, BA1 enable auto precharge; DIS AP = disable auto precharge. Note: PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the ...
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Figure 13: PRECHARGE Command RAS# CAS# Address BA0, BA1 1. If A10 is HIGH, bank address becomes “Don’t Care.” Note: BURST TERMINATE The BURST TERMINATE command is used to truncate READ bursts with auto pre- charge disabled. The most recently ...
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... SELF REFRESH The SELF REFRESH command is used to place the device in self refresh mode; self re- fresh mode is used to retain data in the memory device while the rest of the system is powered down. When in self refresh mode, the device retains data without external clock- ing. The SELF REFRESH command is initiated like an AUTO REFRESH command, except that CKE is disabled (LOW). After the SELF REFRESH command is registered, all inputs to the device become “ ...
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Truth Tables Table 18: Truth Table – Current State Bank n – Command to Bank n Notes 1–6 apply to all parameters in this table Current State CS# RAS# Any Idle ...
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The states listed below must not be interrupted by any executable command; DESELECT 6. All states and sequences not shown are illegal or reserved. 7. Not bank-specific; requires that all banks are idle, and bursts are not in progress. ...
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Table 19: Truth Table – Current State Bank n – Command to Bank m (Continued) Notes 1–6 apply to all parameters in this table Current State CS# RAS# Read (with auto L L precharge ...
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AUTO REFRESH and LOAD MODE REGISTER commands can only be issued when all 5. All states and sequences not shown are illegal or reserved. 6. Requires appropriate DM masking WRITE command can be applied after the completion ...
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Table 20: Truth Table – CKE Notes 1–4 apply to all parameters in this table Current State CKE Active power-down L Deep power-down L Precharge power-down L Self refresh L Active power-down L Deep power-down L Precharge ...
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State Diagram Figure 15: Simplified State Diagram Power Power on applied PRE PREALL LMR LMR EMR WRITE WRITE A PRE ACT = ACTIVE AREF = AUTO REFRESH BST = BURST TERMINATE CKEH = Exit power-down CKEL = Enter power-down DPD ...
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Initialization Prior to normal operation, the device must be powered up and initialized in a prede- fined manner. Using initialization procedures other than those specified will result in undefined operation. If there is an interruption to the device power, the ...
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Figure 16: Initialize and Load Mode Registers ( ( ) ) DDQ CK LVCMOS HIGH LEVEL ( ( ) ) CKE ( ( ) ...
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Figure 17: Alternate Initialization with CKE LOW ( ( ) ) DDQ CK LVCMOS ( ( CKE LOW level ) ) ( ( ) ...
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... Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait quent operation ...
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READ or WRITE command. Burst lengths locations are available for both sequential and interleaved burst types. When a READ or WRITE command is issued, a block ...
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Table 21: Burst Definition Table (Continued) Burst Length Starting Column Address ...
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Figure 19: CAS Latency Command Command Operating Mode The normal operating mode is selected by issuing a LOAD MODE REGISTER command with bits A[n:7] each set to zero, and bits A[6:0] set to the desired values. All other combinations of ...
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Extended Mode Register The EMR controls additional functions beyond those set by the mode registers. These additional functions include drive strength, TCSR, and PASR. The EMR is programmed via the LOAD MODE REGISTER command with BA0 = 0 and BA1 ...
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... Partial-Array Self Refresh For further power savings during self refresh, the partial-array self refresh (PASR) fea- ture enables the controller to select the amount of memory to be refreshed during self refresh. The refresh options include: • Full array: banks and 3 • One-half array: banks 0 and 1 • ...
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Status Read Register The status read register (SRR) is used to read the manufacturer ID, revision ID, refresh multiplier, width type, and density of the device, as shown in Figure 22 (page 58). The SRR is read via the LOAD ...
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... Reserved Notes: 1. Reserved bits should be set to 0 for future compatibility. 2. Refresh multiplier is based on the memory device on-board temperature sensor. Re- PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 S12 S11 ...
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Bank/Row Activation Before any READ or WRITE commands can be issued to a bank within the device, a row in that bank must be opened. This is accomplished via the ACTIVE command, which selects both the bank and the row ...
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READ Operation READ burst operations are initiated with a READ command, as shown in Figure 11 (page 38). The starting column and bank addresses are provided with the READ com- mand, and auto precharge is either enabled or disabled for ...
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Figure 23: READ Burst T0 CK# CK Command READ Address Bank a, Col n DQS DQ T0 CK# CK Command ...
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Figure 24: Consecutive READ Bursts T0 CK# CK Command READ Bank, Address Col n DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS Notes (if 4, the ...
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Figure 25: Nonconsecutive READ Bursts T0 CK# CK Command READ Bank, Address Col n DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS Notes (if burst is ...
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Figure 26: Random Read Accesses T0 CK# CK Command READ Bank, Address Col n DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS Notes (if 4, ...
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Figure 27: Terminating a READ Burst T0 CK# CK Command 1 READ Bank a, Address Col n DQS CK# CK Command 1 READ Bank a, Address Col n DQS ...
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Figure 28: READ-to-WRITE T0 CK# CK Command 1 READ Bank, Address Col n DQS 3 CK# CK Command 1 READ Bank, Address Col n DQS 3 the cases shown (applies ...
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Figure 29: READ-to-PRECHARGE T0 CK# CK Command 1 READ Banka, Address Col n DQS DQ4 T0 CK# CK Command 1 READ Banka, Address Col n DQS interrupted burst 16. ...
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Figure 30: Data Output Timing – CK# LDQS DQ (Last data valid (First data no longer valid) DQ (Last data valid) DQ (First data no longer valid) DQ[7:0] and LDQS, collectively UDQS DQ ...
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Figure 31: Data Output Timing – T1 CK# CK DQS0/DQS1/DQS2/DQS3 4 DQ (Last data valid (First data no longer valid) DQ (Last data valid) DQ (First ...
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Figure 32: Data Output Timing – T0 CK# CK Command READ NOP DQS or LDQS/UDQS 2 All DQ values, collectively 3 1. Commands other than NOP can be valid during this cycle. Notes transitioning after DQS transitions define ...
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... Figure 33 (page 72) (this timing applies to all WRITE operations). Input data appearing on the data bus is written to the memory array subject to the state of data mask (DM) inputs coincident with the data registered LOW, the corre- sponding data will be written registered HIGH, the corresponding data will be ignored, and the write will not be executed to that byte/column location ...
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Data for any WRITE burst can be truncated by a subsequent PRECHARGE command, as shown in Figure 43 (page 81) and Figure 44 (page 82). Note that only the data-in pairs that are registered prior to the any subsequent data-in ...
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Figure 34: Write – DM Operation CKE Command 1 ACTIVE NOP Row Address A10 Row BA0, BA1 Bank ...
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Figure 35: WRITE Burst Command Address t DQSS (NOM) t DQSS (MIN) t DQSS (MAX uninterrupted burst shown. Notes: 2. A10 is LOW with the WRITE command (auto precharge is disabled PDF: 09005aef82d5d305 ...
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Figure 36: Consecutive WRITE-to-WRITE T0 CK Command WRITE Bank, Address Col b t DQSS (NOM) DQS Each WRITE command can be to any bank. Notes uninterrupted burst shown. ...
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Figure 38: Random WRITE Cycles T0 CK# CK 1,2 Command WRITE Bank, Address Col b t DQSS (NOM) DQS DQ 3,4 DM Notes: 1. Each WRITE command can be to any bank. 2. Programmed ...
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Figure 39: WRITE-to-READ – Uninterrupting T0 CK Command 2,3 WRITE Bank a, Address Col DQSSnom DQSS DQS DQSSmin DQSS DQS DQSSmax DQSS DQS ...
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Figure 40: WRITE-to-READ – Interrupting T0 CK# CK Command 1,2 WRITE Bank a, Address Col DQSS (NOM) DQSS 4 DQS DQSS (MIN) DQSS 4 DQS ...
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Figure 41: WRITE-to-READ – Odd Number of Data, Interrupting T0 CK Command 2 WRITE Bank a, Address Col DQSS (NOM) DQSS 4 DQS DQSS (MIN) DQSS 4 DQS 5 D ...
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Figure 42: WRITE-to-PRECHARGE – Uninterrupting T0 CK Command 2,4 WRITE Bank a, Address Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS ...
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Figure 43: WRITE-to-PRECHARGE – Interrupting T0 CK Command 2 WRITE Bank a, Address Col DQSS (NOM) DQSS 5 DQS DQSS (MIN) DQSS 5 DQS ...
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Figure 44: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting T0 CK Command 2 WRITE Bank a, Address Col b t DQSS (NOM) t DQSS 5, 6 DQS DQSS (MIN) t DQSS 5, 6 ...
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PRECHARGE Operation The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time ( mines whether one ...
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Concurrent Auto Precharge This device supports concurrent auto precharge such that when a READ with auto pre- charge is enabled or a WRITE with auto precharge is enabled, any command to another bank is supported, as long as that command ...
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Figure 45: Bank Read – With Auto Precharge CKE Command NOP ACTIVE Address Row A10 Row BA0, ...
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Figure 46: Bank Read – Without Auto Precharge CKE Command 1 ACTIVE NOP Row Address A10 Row BA0, ...
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Figure 47: Bank Write – With Auto Precharge CKE Command 4 NOP ACTIVE Address Row A10 Row BA0, ...
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Figure 48: Bank Write – Without Auto Precharge CKE Command 1 NOP ACTIVE Address Row A10 Row BA0, ...
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AUTO REFRESH Operation Auto refresh mode is used during normal operation of the device and is analogous to CAS#-BEFORE-RAS# (CBR) REFRESH in FPM/EDO DRAM. The AUTO REFRESH com- mand is nonpersistent and must be issued each time a refresh is ...
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SELF REFRESH Operation The SELF REFRESH command can be used to retain data in the device while the rest of the system is powered down. When in self refresh mode, the device retains data without external clocking. The SELF REFRESH ...
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Figure 50: Self Refresh Mode T0 CK 1,2 CKE Command NOP Address DQS Clock must be stable, cycling within specifications by Ta0, ...
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Figure 51: Power-Down Entry (in Active or Precharge Mode) RAS#, CAS#, WE# RAS#, CAS#, WE# PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM CK# CK CKE CS# Or CS# Address BA0, BA1 Don’t Care ...
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... Deep Power-Down Deep power-down (DPD operating mode used to achieve maximum power reduc- tion by eliminating power to the memory array. Data will not be retained after the device enters DPD mode. Before entering DPD mode the device must be in the all banks idle state with no activity on the data bus ( LOW with RAS# and CAS# HIGH at the rising edge of the clock while CKE is LOW ...
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Figure 53: Deep Power-Down Mode T0 CK# CK CKE 1 Command NOP All banks idle with no activity on the data bus 1. Clock must be stable prior to CKE going HIGH. Notes: 2. DPD = deep power-down. 3. Upon ...
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Clock Change Frequency One method of controlling the power efficiency in applications is to throttle the clock that controls the device. The clock can be controlled by changing the clock frequency or stopping the clock. The device enables the clock ...
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Revision History Rev. I, Production – 12/09 • Changed all Rev. H, Production – 03/09 • Added a note to the • Added a second paragraph to SELF REFRESH (page 41). • Added Rev. G, Production – 02/09 • Removed ...
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Rev. C, Production – 03/08 • Added programmable burst length “Features” • Updated example cycle time Figure 1: “512Mb Mobile DDR Part Numbering” • Corrected Idd0 unit value Table 9, “Idd ...
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Removed 70°C and 15°C values from Table 9: “Idd6 Specifications and Conditions” as they are redundant and are shown in Figure 9: “Typical Idd6 Curves” • Changed the following specification: tRC -75 to 67.5ns, and removed note 21 from ...