MT46H16M32LFCX-5:B Micron Technology Inc, MT46H16M32LFCX-5:B Datasheet - Page 43

• Manufacturer Part Number: MT46H16M32LFCX-5:B
• Description: IC DDR SDRAM 512MBIT 90VFBGA
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H16M32LFCX-5:B

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 512M (16M x 32)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Organization: 16Mx32
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 6.5/5ns
• Maximum Clock Rate: 200MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 125mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 19: Truth Table – Current State Bank n – Command to Bank m
Notes 1–6 apply to all parameters in this table
PDF: 09005aef82d5d305
512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN
Current State
Any
Idle
Row activating,
active, or pre-
charging
Read (auto pre-
charge disabled)
Write (auto pre-
charge disabled)
CS#
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS#
10. READs or WRITEs listed in the Command/Action column include READs or WRITEs with
11. Requires appropriate DM masking.
12. A WRITE command can be applied after the completion of the READ burst; otherwise, a
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
5. The states listed below must not be interrupted by any executable command; DESELECT
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle, and bursts are not in progress.
8. May or may not be bank-specific; if multiple banks need to be precharged, each must be
9. Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of
Read with auto-precharge enabled: Starts with registration of a READ command with
auto precharge enabled and ends when
be in the idle state.
Write with auto-precharge enabled: Starts with registration of a WRITE command with
auto precharge enabled and ends when
will be in the idle state.
or NOP commands must be applied on each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when
is met. After
Accessing mode register: Starts with registration of a LOAD MODE REGISTER command
and ends when
banks idle state.
Precharging all: Starts with registration of a PRECHARGE ALL command and ends when
t
in a valid state for precharging.
bank.
auto precharge enabled and READs or WRITEs with auto precharge disabled.
BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE com-
mand.
RP is met. After
CAS#
X
H
X
H
H
H
H
H
H
L
L
L
L
L
L
WE#
t
RFC is met, the device will be in the all banks idle state.
X
H
X
H
H
H
H
H
H
L
L
L
L
L
L
t
MRD has been met. After
t
RP is met, all banks will be in the idle state.
Command/Action
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
Any command supported to bank m
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
43
512Mb: x16, x32 Mobile LPDDR SDRAM
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
t
RP has been met. After
RP has been met. After
t
MRD is met, the device will be in the all
© 2004 Micron Technology, Inc. All rights reserved.
t
t
RP is met, the bank will
RP is met, the bank
Truth Tables
Notes
7
t
RFC