MT46H16M32LFCX-5:B Micron Technology Inc, MT46H16M32LFCX-5:B Datasheet - Page 93

IC DDR SDRAM 512MBIT 90VFBGA

MT46H16M32LFCX-5:B

Manufacturer Part Number
MT46H16M32LFCX-5:B
Description
IC DDR SDRAM 512MBIT 90VFBGA
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet

Specifications of MT46H16M32LFCX-5:B

Format - Memory
RAM
Memory Type
Mobile DDR SDRAM
Memory Size
512M (16M x 32)
Speed
200MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.95 V
Operating Temperature
0°C ~ 70°C
Package / Case
90-VFBGA
Organization
16Mx32
Density
512Mb
Address Bus
15b
Access Time (max)
6.5/5ns
Maximum Clock Rate
200MHz
Operating Supply Voltage (typ)
1.8V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
1.95V
Operating Supply Voltage (min)
1.7V
Supply Current
125mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT46H16M32LFCX-5:B
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT46H16M32LFCX-5:B
Manufacturer:
MICRON
Quantity:
20 000
Part Number:
MT46H16M32LFCX-5:B TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Figure 52: Power-Down Mode (Active or Precharge)
Deep Power-Down
PDF: 09005aef82d5d305
512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN
Command
Address
DQS
CK#
CKE
DM
DQ
CK
No read/write
access in progress
t
t
t
IS
IS
IS
Valid
Valid
Notes:
T0
t
t
IH
t
2
IH
IH
Deep power-down (DPD) is an operating mode used to achieve maximum power reduc-
tion by eliminating power to the memory array. Data will not be retained after the
device enters DPD mode.
Before entering DPD mode the device must be in the all banks idle state with no activity
on the data bus (
LOW with RAS# and CAS# HIGH at the rising edge of the clock while CKE is LOW. CKE
must be held LOW to maintain DPD mode. The clock must be stable prior to exiting
DPD mode. To exit DPD mode, assert CKE HIGH with either a NOP or DESELECT com-
mand present on the command bus. After exiting DPD mode, a full DRAM initialization
sequence is required.
t
CK
1.
2. If this command is a PRECHARGE (or if the device is already in the idle state), then the
3. No column accesses can be in progress when power-down is entered.
power-down
t
HIGH at Ta2 (exit power-down).
power-down mode shown is precharge power-down. If this command is an ACTIVE (or if
at least 1 row is already active), then the power-down mode shown is active power-down.
t
CKE applies if CKE goes LOW at Ta2 (entering power-down);
IS
Enter
mode
NOP
T1
3
t
CH
Must not exceed refresh device limits
t
RP time must be met). DPD mode is entered by holding CS# and WE#
t
CL
T2
(
(
(
(
(
(
(
(
)
(
)
(
)
(
)
(
)
(
)
)
)
)
)
)
)
)
(
(
(
(
(
(
(
)
)
)
)
)
(
)
)
(
(
(
(
(
)
)
)
)
)
)
t
CKE
93
512Mb: x16, x32 Mobile LPDDR SDRAM
Ta0
Micron Technology, Inc. reserves the right to change products or specifications without notice.
power-down
mode
NOP
Ta1
Exit
t
t
XP
CKE
1
1
© 2004 Micron Technology, Inc. All rights reserved.
Valid
Valid
Ta2
t
XP applies if CKE remains
Power-Down
Don’t Care
Tb1

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